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Subject: Regarding setting relative propagation delay
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kingshar
Posts: 33
Online: User is Offline
5/16/2008 2:31 AM  
Hi , Can anyone explain how to set relative propagation delay constraint in constraint manager. Is there any guidelines on how to set other constraints using constraint manager. Thanks in advance, Kingshar
vealmic@uk.ibm.com
Posts: 23
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6/02/2008 9:41 AM  
Realtive propagation delays are all about creating matched groups (MGs). A group of objects with either a matched length, or propagation delay.

An object can be a net, an xnet (2 nets joined by a passive with an espice model) or a pin pair

Constraint manager (CM) allows you to specify one object as the target, then all other onjects in the MG must match this. Each of the other objects may be given a delta and a tolerance.

Finally you need to decide on the scope of the MG.

Let's take a data bus with source series termination as an example. Lets say that you create a EC Set with the following items in a MG.
1. The pin pair defining the link from the uP to the terminator.
2. The pin pair defining the link from the terminator to the memory device.

You then apply the EC set to all the xnets in the data bus.

Setting the MG scope to Local.
Within each Xnet, the pin pairs 1. and 2. will match.
From xnet to xnet, the pin pairs will not match.
So the terminator will be half way along the xnet for every bit in the bus, but the bits will be different lengths.

Setting the MG scope to global.
Within each Xnet, the pin pairs 1. and 2. will match.
From xnet to xnet, the pin pairs will also match.
So the terminator will be half way along the xnet for every bit in the bus, and every bit in the bus will be the same length.

There are two other MG Scopes, bus (>15.7) and class (>16.0). This presentation gives an example of how bus scope works. Class scope is similar, and would avoid the need to redraw the schematic.
http://www.cdnusers.org/community/allegro/Resources/kits_designin/memory/stp_cdnliveemea07_ddrconstraints_veal.pdf

Good luck,
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Forums > Silicon-package-board > PCB Design > Regarding setting relative propagation delay


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