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Subject: Constraint Manager
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Jackie
Posts: 22
Online: User is Offline
5/27/2008 12:44 PM  
All, I am using Allegro Performance L V16.01 with the latest hotfix. I am trying to set up the CM and am having quite a few problems. I'm not sure if I am not using it properly or if it just doesn't work the way I want it to. I have Net classes called POWER and RF. I have it set up so the to contraint to be 25mils - which works fine. But I also want to to be 5 mil. Is this possible? I'm trying to set it up like this but whenever I override the to 5 mils the software generates the to as 5 mils. I have RF shapes coming off pins to get the proper taper from a small pin to the wider RF trace. Because of this, I have many DRC's on SOIC's and similar parts. Any ideas, anyone? (The referenced Spacing CSet for Power is Power and for RF, RF) Thanks, Jackie
Jackie
Posts: 22
Online: User is Offline
5/27/2008 12:51 PM  
Wow, when I posted this I had brackets around the wording to make it a bit more legible, but when I submitted, it deleted everything within the brackets. Sorry about that.

I will try again.
I have it set up so the PWER shape to RF lines contraint to be 25mils - which works fine.
But also want the RF shape to POWER lines and smd pins to be 5 mils.
Whenever I override the RF shape to POWER lines and smd pins, the software generates the POWER shape to RF lines as 5 mils.


Jackie
redwire
Posts: 73
Online: User is Offline
5/27/2008 7:24 PM  
Still ramping up on 16.01 here...but it looks like you need to set up some net class to net class spacings... then you should be able to do what you want.

If possible, zip up your design and post it here. Might be faster to solve.
BillZ_EMA
Posts: 51
Online: User is Offline
5/28/2008 5:35 AM  
Hi,
I don't understand excatly what your trying to do. But I'll see if I can help. You can only apply one rule at a time.
You can not have a 25 mil space and a 5 mil space. Since you have performamnce you can have a region rule.
25 mil space in the general board area and a 5 mil space around the component. You can set up class to class rules.
Is this helping? Also what is the same net drc set to? You might want to turn it off while routing.

Regards,
BillZ
EMA Design Automation
Jackie
Posts: 22
Online: User is Offline
5/28/2008 6:56 AM  
Thanks so much for your replies.
It turns out that it doesn't do what I want, which is to have the net class-class space - line constraint for power set to 25mils and the space - line constraint for RF set to 5mils. So I have to try to come up with something else. Either I have to put regions around all of the RF parts that have shapes coming off the pins (there are a lot of them!) or maybe add a new spacing constraint set. I'm working with Cadence Support on this.

Thanks again for your help,
Jackie
cadpro2k
Posts: 45
Online: User is Offline
5/28/2008 9:09 PM  
You can also work with each shape's parameters to get the settings you want. Once you have 1 correct (visually) it'll be pretty easy to do the others. I've done this a time or 2.

Good day.
Mitch
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Forums > Silicon-package-board > PCB Design > Constraint Manager


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