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Subject: [help] about ConceptHDL signal name
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zxpchx
Posts: 6
Online: User is Offline
6/30/2008 12:54 AM  
Hi,all. in the conceptHDL the signal name is displayed "UN$2$BC847BF$I93$B"(FIG:software automatic generate signal name.JPG),but after PXL, in the PSTXNET.dat, the signal name is "UNNAMED2BC847BFI93B"(FIG:pstxnet.JPG). I want to know why like this? I hope the signal name is"UN2BC847BFI93B".How to do?








cdavies
Moderator
Posts: 55
Online: User is Offline
7/01/2008 8:36 AM  
This a function of the packager. It is unlikely that Cadence will change this behavior. There is a property on the schematic that can be seen in expanded mode (CDS_PHYS_NET_NAME) that will show the name that was passed to Allegro. You must have an environment variable set (SHOW_CDS_PROPS=TRUE) in order for this to work.

Hope this helps.
Charlie Davies
zxpchx
Posts: 6
Online: User is Offline
7/02/2008 12:11 AM  
firstly, thank you Mr./Ms. Charlie davies.

you know that in the setting "net name length"("setup--tools--packager-xl-->layout), we can not set very short or very long,because our PCB software(not allegro) is limited the net name length 31.

we think that "UN......"(2character) is very clear, not need useing "UNNAMED......"(7character).
Concept SCALD's net name is used "UN......",but ConceptHDL's "UNNAMED......". why is it like this one?

in the packager-xl, how to set can we get "UN......"?
cdavies
Moderator
Posts: 55
Online: User is Offline
7/02/2008 2:36 PM  
I don't know of anyway to eliminate the UNNAMED in the net name. Set the net name length to be equal to what your layout tool can support should result in unique signal names. I suspect that Cadence thought about that when they came up with the algorithm. If that doesn't work, I would suggest contacting Cadence and opening an SR.


Hope this helps.
Charlie Davies
rbennett
Posts: 27
Online: User is Offline
7/02/2008 2:47 PM  
Set the variable:

UNNAMED_NET_GEN to 'OFF'
rbennett
Posts: 27
Online: User is Offline
7/02/2008 2:54 PM  
Set this Variable in the project CPM area:

START_CONCEPTHDL
.
.
UNNAMED_NET_GEN to 'OFF'
.
.
END_CONCEPTHDL
rbennett
Posts: 27
Online: User is Offline
7/02/2008 3:10 PM  
sorry... make sure you do NOT include the 'to' above....:

START_CONCEPTHDL
.
.
UNNAMED_NET_GEN 'OFF'
.
.
END_CONCEPTHDL
zxpchx
Posts: 6
Online: User is Offline
7/02/2008 9:49 PM  
Hi,Mr./Ms. Charlie davies and rbennett. thank you help me. I add the Variable (UNNAMED_NET_GEN 'OFF')in my project CPM. After PXL, it is the same as before. why? Thanks.
zxpchx
Posts: 6
Online: User is Offline
7/02/2008 9:49 PM  
Hi,Mr./Ms. Charlie davies and rbennett. thank you help me. I add the Variable (UNNAMED_NET_GEN 'OFF')in my project CPM. After PXL, it is the same as before. why? Thanks.
zxpchx
Posts: 6
Online: User is Offline
7/29/2008 12:27 AM  
Hi, all.
from the concepthdl training doc, I think that input file:Verilog.V file decides wire's signal name. i only modify the wire's netname, after PXL,finally, i find that the netname is changed in pstxnet.dat,but the verilog.v is regenerated again, the wire's netname is renamed to UNNAME....why? Thanks,
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Forums > Silicon-package-board > PCB Design > [help] about ConceptHDL signal name


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