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Subject: LVS error for Dummy MOS
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isazul
Posts: 26
Online: User is Offline
3/12/2008 6:32 PM  
Hi everybody.

I used Dummy Mos in my layout in order to have a better Matching. But when running LVS, DIVA generate error because it consider dummy MOS  as real.  There is a layer to specify dummy poly in order to avoid error due to dummy?? or there is another way to avoid that error?

I have tha same problem with ctm dummy, even if I put ctmdmy layer

thanks for your help!!
viswanadhbabu
Posts: 16
Online: User is Offline
3/12/2008 8:53 PM  
HI ,
In fabrication "Dummy mos" layer will take as metal layer . While Doing Lvs Dummy mos layer will consider as Metal layer. if Two metals unintentionally joined with dummy mos ,then tool will treat as a short.
In order to avoid this problem run DRC (it will take care of Dummy mos rules). While filling Dummy mos kept the Space to Metal layers.
isazul
Posts: 26
Online: User is Offline
3/12/2008 10:22 PM  
Hi;
In fact LVS see dummy poly as Net. I connected the 2 sides of the "dummy poly" to VDD for a PMos and to VSS for an NMos.
To which potential do you connect your dummy Poly?

It's correct when I run a DRC, There is No error.
viswanadhbabu
Posts: 16
Online: User is Offline
3/12/2008 10:43 PM  
Dummy must be connected to ground to avoid noise.

Or else

Could you mention the lvs error displayed by tool.


kvb
adbeckett
Posts: 248
Online: User is Offline
3/13/2008 12:27 AM  
In Diva you can put rules in the LVS rules to prune devices. Look in the Diva manual for information about pruning.

Better still, put the dummy devices in the schematic too - that way you can check that they're actually present...

Andrew.
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Forums > Custom IC > Custom IC Physical Design > LVS error for Dummy MOS


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