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Subject: Disabling Timing checks between clocks
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arunrach
Posts: 17
Online: User is Offline
7/19/2008 6:05 PM  
Hi,

I am running timing analysis on my design in Encounter. There are many violations reported on paths between clock domains.

I need to set a false path between two clocks. Is there a way to do that? Right now Encounter expects me to explicitly specify a false path from every start point in one clock to every end point in the other clock domain. THis is proving to be tedious since I blindly want to disable all paths from one clock to another.

Please let me know if you know how to solve this.

Thanks,
Arun
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Forums > Custom IC > Custom IC Physical Design > Disabling Timing checks between clocks


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