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Subject: Bus delimiter mismatch
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arunrach
Posts: 17
Online: User is Offline
7/15/2008 8:20 AM  
Hi,

I notice that verilog interprets [] as a valid bus delimiter. However, Cadence ICFB environment understands <> as a valid delimiter. I generate the gds using Encounter with this verilog netlist. After importing the gds I manually change the delimiter for all the pins in ICFB.

This is proving to be time consuming when there are many signals. Any ideas (skill script etc) to make this process less tedious?

Thanks in advance for the help.
Arun
rairaj
Posts: 17
Online: User is Offline
7/15/2008 8:24 AM  
Arun,

In Stream IN form there is "Options" button. Click on that and then there is a field that you need to enable:
Replace [] with <>

RR
arunrach
Posts: 17
Online: User is Offline
7/15/2008 8:32 AM  
Thanks RR.
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Forums > Custom IC > Shared code - SKILL > Bus delimiter mismatch


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