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Subject: generated_clock issues
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arunrach
Posts: 17
Online: User is Offline
7/18/2008 3:18 PM  
Hi,

I am using encounter for a design synthesizd by Build Gates. I see that if I feed the following constraint using read_dc_script in Build Gates, it works fine:

create_clock [get_ports {CLK300_RX}]  -name CLK300_RX -period 2.5 -waveform {0 1.25}

create_generated_clock -name CLK75_RX -source [get_ports {CLK300_RX}] -divide_by 4 [get_pins {STR_RX_blk/cnt4_reg_1/Q}]

This when read in Encounter creates a generated clock with the warning "Master clock source not found". And the period assigned to this clock is {0 0} when I do report clock waveform. The generated clock constraint got recognized in BG but is not getting recognized in Encounter.

I need four generated clocks in my design. How should I go about this. Any help on this would be extremely helpful.

Thanks,
Arun
adbeckett
Posts: 248
Online: User is Offline
7/21/2008 1:33 AM  
Well, posting a question about Build Gates in the SKILL forum is not likely to get you an answer...

BTW, you should be migrating questions across to the forums on www.cadence.com communities, as cdnusers.org will be retired shortly.

Regards,

Andrew.
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Forums > Custom IC > Shared code - SKILL > generated_clock issues


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