If you are using or plan to use RMW type of memory operation in RTL and then want to compile memory to Xtreme using +mc, then please keep in mind following-

RMW is typically used to implement bitwise masking in the following way, e.g.

always@(posedge write_clk)
  mem[write_addr] <= (bitmask & din) | (~bitmask & mem[write_addr]);

If you use this style, then the memory generated by MC will be quite complicated, using axis_behctrl and a behavioral statemachine.

Instead, use the following method for achieving the same functionality:

assign write_dout = mem[write_addr]
always@(posedge write_clk)
  mem[write_addr] <= (bitmask & din) | (~bitmask & write_dout);

The above is correctly transformed to simple axis_smem with one async. read port and a sync. write port. This is easier to debug and faster to simulate.

The above recommendation only applies to a sync. write port.

You can always look at MC generated memories by using +mcdbg switch (which creates AXIS_MC.DEBUG text file) to ensure memories are transformed to their simple axis_smem forms and not having to use axis_behctrl.

-ashutosh