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hubertx
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2/07/2007 10:25 AM
Can I force or probe a signal in vhdl module from verilog top testbench? I heard some simulator has its own way to do that easily, can you give me a example to do that with ncsim?

Harlinator
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2/07/2007 12:28 PM
Some of the more recent versions of IUS (ncsim) will take '.' as the hierarchical separator through a mixed language hierarchy. In older versions, you would have to guess at when to use '.' and ':' through a hierarchical reference. If you're not sure, bring up the design browser and scope down into the module you are interested in and the design browser will show you the hierarchical path with the appropriate delimiters. Let us know if this doesn't answer your question. Harlin!

Harlin L. Hamilton Jr. Sr. Consulting Engineer, Cadence Design Systems harlinh@cadence.com

tom paulson
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2/09/2007 9:28 AM
The testbench is verilog and the design is VHDL. So we instantiate the VHDL design (em0) at the verilog top level and force signals as follows: signal -force em0__ec0__fp0__flport_1__secnt_mclr 0 (this is for the Palladium) hope that helps!

Harlinator
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2/09/2007 10:25 AM
Hey, Tom! Also, in Palladium, once it goes through design import, there's no language difference (in reality, after HDLICE it's generally all verilog netlists). You can set the delimiterRule to verilog and then use '.' as hierarchical delimiter for the entire design. Using '.' is even more advantageous when you start with a gate-level netlist that usually contains instance names like '\a.b.c.dΎ]_456' or the like. Those things get ugly real fast. Harlin!

Harlin L. Hamilton Jr. Sr. Consulting Engineer, Cadence Design Systems harlinh@cadence.com

tom paulson
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2/09/2007 10:30 AM
hey Harlin...we have used VHDL for so long we just haven't changed. When we evaluated assertions on the Palladium, we did use the "." as the separator...thanks!

venkatreddy
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7/09/2008 9:39 PM
Hi harlimitor ! I too have the same problem. How to force or deposit or proble a signal in VHDL module from verilog top testbench. While simulating I am using init.do as an input, in which I have digit_inst ----> verilog top file dut_inst ------> vhdl design pll_inst -------> vhdl design counter_inst ----> vhdl design And the design hierarchy goes like this from digit_inst. I have given deposit digit_inst.dut_inst:testsite:ba8p:hc:pll:pllcalib:divrefclk = 1'b0 *E,PNOOBJ: path element could not be foung : pll Am getting the error as given above. please help me solve this problem, Am new to Cadence tool. Thank you in advance Venkatreddy

douge
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7/10/2008 6:14 AM
What you are describing is an out of module reference (OOMR) originating in Verilog and terminating in VHDL. This is not directly supported. From the mixed language reference manual "Out-of-module references (OOMR) from Verilog modules must terminate in a Verilog module. The OOMR can go through VHDL hierarchies, but cannot reference a VHDL signal. In other words, a hierarchical path in a Verilog model must end with a name that refers to a Verilog object or scope." Perhaps you can use $nc_mirror, $nc_deposit, $nc_force, $nc_release. See the ncvlog reference manual chapter 19.

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