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Subject: Problem Linking mixed vhdl-verilog env with specman
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rmalvi
Posts: 1
Online: User is Offline
4/27/2007 6:17 AM  

Hi All,

            I am hoping someone can help me with this problem I am having:

1.      RTL is vhdl, top level testbench is Verilog and verification env is specman.

2.      I am using Specman 5.0 with MTI Vhdl 6.1f_p2 on Amd64 running linux.

 

My compilation & Link Steps Are:

1.      specman –c “load top.e; write stubs –verilog; write stubs –qvh;”

2.      sn_compile.sh –shlib –exe top.v

3.      vlib work

4.      vcom specman_qvh.vhd –f file_list.f

5.      vlog specman.v top.v

6.      specview –p “load test.e; test” –sio vsim –keepstdout –pli $(SPECMAN_HOME)/linux/libmti_sn_boot.so top specman

 

When I run this, all works well until MTI tries to load the libmti_sn_boot.so and it complains that it is not able to load the shared object.

·         Is there a different shared object that needs to be loaded for Amd64?

·         Are the steps I am using correct?

 

Any help with this is greatly appreciated.

Thanks,

Rahul

 
ajeetha
Posts: 97
Online: User is Offline
4/30/2007 8:02 AM  
Rahul,
     Are you using 64 bit versions of MTI & Specman? If so maybe you need to use a different libmti_sn_boot.so file. Look for "*64*" files inside Specman install dir.

Regards
Ajeetha, CVC
www.noveldv.com
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Forums > Functional Verification > Simulation, Acceleration, Emulation > Problem Linking mixed vhdl-verilog env with specman


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