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Forums > Functional Verification > Assertion-Based Verification and Formal Analysis

Subject: interdependent constraints
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rajendraorpe
Posts: 8
Online: User is Offline
7/11/2007 10:21 PM  
Hi,
  In my design there are say two signals apart from other signals.  req_val, req_cntl.
  The req_cntl is only valid if the req_val is asserted or say high.

  For some assertion say I don't want req_val to get asserted. Hence I constrain it to 0 (low).

  So does it make sense to leave req_cntl unconstrained especially if the width of req_cntl is high(say 5).

  Or to be specific leaving req_cntl unconstrained, will IFV try to explore the assertions for the different values of req_cntl (i.e. 2 ** 5) values?

thanks,
Rajendra
 
jmueller
Posts: 14
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7/12/2007 1:00 AM  
Hi Rajendra,

Yes, IFV will consider every possible value for any input or undriven net, i.e. 2**5 different values for req_cntl.

Regards,
Joerg.
rajendraorpe
Posts: 8
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7/12/2007 1:06 AM  
thanks Joerge.
So you mean better constrain req_cntl as well, don't you?
jmueller
Posts: 14
Online: User is Offline
7/12/2007 2:03 AM  
Hi,

No. You say "The req_cntl is only valid if the req_val is asserted", so if it is invalid it should not matter what value you see on req_cntl, since your design should not consume it. I would leave it unconstrained.

Joerg.
rajendraorpe
Posts: 8
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7/12/2007 2:33 AM  
Hi Joerge,
You are correct my design will not consume it.
However IFV tool will unnecessarily try these redundant 2**5 possibilities for converging to proof of the property.

In short if IFV tries 2000 different possibilities for design then it will try 2000 * (2**5) possibilities because of these false scenarios which anyway will not affect the verification.
Am I correct?
And if the design is complex enough then the properties that would have converged with constrained req_cntl may not converge to any proof at all.

thanks,
Rajendra
jmueller
Posts: 14
Online: User is Offline
7/12/2007 2:52 AM  
Hi Rajendra,

no, formal algorithms do not work that way. Leaving req_cntl unconstrained makes it to a "don't care", which is an easier to satisfy requirement for the tool than an explicit constraint on the same signal. And it does not do 2**5 operations, but only one which considers 2**5 values.

Having said that, constant pin constraints can lead to removal of logic, which can improve performance in some cases as well.

Joerg.
rajendraorpe
Posts: 8
Online: User is Offline
7/12/2007 3:01 AM  
Hi Joerg,
That makes it clear. I understand.

thanks for answering the queries patiently.

Rajendra
TAM
Posts: 56
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7/12/2007 7:24 AM  
I'd like to add my own two cents to the discussion. I think that there are three points to consider.

1. Leaving the vector unconstrained will increase the state space that IFV needs to consider. But IFV is very good at optimizing the algorithms for exploring this state space. It is very unlikely that leaving the vector unconstrained will add 2**5 unique iterations to its analysis. If the design is such that req_val does disable req_cntl, then IFV will note that fact and those states will not be investigated anyway.

2. Adding constraints adds overhead to each IFV iteration. It is possible to constrain a design to the point where the time taken to satisfy the constraints begins to match the time saved by limiting the state space.

3. This may be the most important point. It may be that in the correct design req_cntl is ignored if req_val is disabled. But the whole purpose of IFV is to find design bugs. Constraining req_cntl will make it impossible for IFV to find a design error where a block does not look at req_val before looking at req_cntl.

I can't really say what is going on behind-the-scenes in IFV, so my point number 1 is just my assumption about the way IFV works. But I have seen cases of points number 2 and 3. Especially point 3, you can constrain yourself right by some design bugs that IFV would otherwise have caught.
rajendraorpe
Posts: 8
Online: User is Offline
7/12/2007 7:46 AM  
Thanks TAM,
That added to my knowledge.
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