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Forums > Functional Verification > Assertion-Based Verification and Formal Analysis

Subject: Calculating Throughput & hence Band-width
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vlsi_dude
Posts: 55
Online: User is Offline
10/12/2007 9:38 AM  
Hi Guys,
Wanted to calculate the throughput in case of accessing memory.If consecutive write & reads are ther how we can prove that so and so throughput is achieved.need to consider the total time taken for access or how?
Thanks.
darrowchu
Posts: 4
Online: User is Offline
10/19/2007 6:21 PM  
Hello:

You may consider use several cover statements to time the memory access latency using formal analysis. Take single read as an example: we can roughly guess the read latency using following cover properties in SVA and then run formal analysis:

cover_rd_latency_2: cover property (@(posedge clk) read_en ##2 read_vld); (Fail)
cover_rd_latency_3: cover property (@(posedge clk) read_en ##3 read_vld); (Pass)
cover_rd_latency_4: cover property (@(posedge clk) read_en ##4 read_vld); (Fail)

In the above example, we can find single memory read latency is 3 cycles.

We can apply the same technique to time the memory latency/bandwidth for different combinations of consecutive read/write commands.

Hope this helps,
Darrow
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