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mvetromille
Posts: 3
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11/21/2007 10:21 AM
When I synthesize my designs, RTL compiler exchanges the internal signals' names for random ones. Does anyone know if there is a way to keep the internal signals' names? Or, is there a way to map the old names to the new ones? I'll try to explain my problem in a better way. I'm using PSL to verify the functioning of my design and I map internal signals to external ones (using ncmirror) in order to be able to evaluate them in PSL. When I'm using RTL that's ok, but when I have to verify the generated netlist, RTL compiler keeps the port's names but changes the name of some signals. For example, if I map a signal which name is tmod_s in my PSL, after synthesis this signal's name is changed for something like n_25 and my PSL does not work anymore. I've tried the following command before elaboration but I didn't have success: set_attr preserve true -net <netname to be preserved> I've tryied to preserve the signal count_enable_s which is set as following: count_enable_s <= '1' when pre_count_s = conv_unsigned(11,4) else '0'; In fact, observing the elaboration result I realized it was transformed in a MUX, and its output was named to n_26. Is there a way to keep the output with the name count_enable_s instead of n_26?

geryo
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11/21/2007 10:41 AM
OK, I'm not exactly an expert in the matter, but would you not want to verify the "design" at the RTL level using PSL, and then if you do not trust your synthesis tool - or if you had to make changes to the synthesized design manually, then use an equivalence checking tool? Cheers, G.O.

jmueller
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11/22/2007 1:27 AM
Hi mvetromille, Preserving all internal signals would also prevent any structural optimizations during synthesis, so I am not sure if you really want this. However, I can inagine that you are able to preserve at least the port names of internal blocks, not signals, did you try that? If this is possible then the recommendation would be to write properties only using the internal port names. Otherwise the flow breaks. Joerg.

mvetromille
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11/22/2007 7:51 AM
Thank you, Joerg. In fact, I don't know if it would be an impact to my design if I prevent structural optimizations during synthesis. I really need to use the internal signals in my properties instead of the ports. So, not considering the optimization after synthesis, do you know how to preserve the name of some internal signals? Melissa.

ajeetha
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11/22/2007 7:00 PM
Hi Melissa, This is more of a RTL compiler question and perhaps you should ask in the Digital IC forum for synthesis experts comments. As Joerg mentioned, it will be a good idea to write PSL on ports only - especially for those properties expected to be reused at GLS. We make some of these recommendations in our PSL book (see: www.systemverilog.us). Another relevant guideline was to use only Sequential nodes in your PSL code - in your case you are lucky that the combinatorial nodes are still present. We have seen cases where the whole logic gets optimized and the signal is lost. We at CVC have a half-a-day workshop on "ABV beyond RTL" that touches upon this topic very extensively, provides examples on how to handle common synthesis optimizations (like bit blasting etc.). It also provides template flow on how to use an equivalence checker to automate this kind of mapping. Perhaps Conformal can provide a flow for this if you work closely with you Cadence AE. Regards Ajeetha, CVC www.noveldv.com

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