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Forums > Functional Verification > Assertion-Based Verification and Formal Analysis

Subject: forml verification on system level verification
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abna
Posts: 6
Online: User is Offline
1/10/2008 2:22 AM  
Hi all,

I would like to know if you are able to use the formal verification on the system level verification.


Thanks,
TAM
Posts: 56
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1/10/2008 6:32 AM  
Anything is possible. But I believe that the "sweet spot" for which IFV is targeted is at the block level. I took a quick glance at the Cadence web page for formal and they show it being used at the "block/module" and "cluster/block" levels and then simulation taking over for verification of the "full chip".
abna
Posts: 6
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1/16/2008 8:34 AM  
Thanks TAM for your response. 

Have you an idea if there are some examples of system level verification using formal methods. 

Regards,
TAM
Posts: 56
Online: User is Offline
1/16/2008 8:37 AM  
No I don't. The IFV team is recommending that it be used on the block and cluster levels and not recommending it for the system level. If they had examples that worked at that level, I suspect that they'd be publicizing them.
abna
Posts: 6
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1/16/2008 9:03 AM  

Sorry, I make a mistake. In fact, I would like to ask you this question:
Have you an idea if there are some examples of cluster level verification using formal methods. 


Regards,
stephenh
Posts: 77
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1/16/2008 10:05 AM  
Assuming you do a pretty good job of your block-level verification, then system verification is going to be (broadly) a mixture of integration testing and architectural verification. I say this because your block verification should have ensured that blocks behave perfectly when they receive valid inputs, and also that each block feeds valid inputs to its neighbours.

Integration testing is asking "did I connect all the blocks correctly".
For this we have a lot of success using IFV to prove the connections between IP blocks, and to the pads. It's pretty clear what should be tested, and IFV proves if there is any bad MUXing etc pretty fast. In fact we have a combination of Excel sheet and Perl script to do all the property writing for you. All you have to do is list the connection requirements.

Architectural verification is making sure the blocks work in harmony to produce the desired system properties. E.g. "can I play MP3 files at all the supported bit rates".
I can't see much scope for writing PSL / SVA properties for such high-level behaviour, so I would leave that to simulation with some directed or coverage-driven tests.

Hope this helps.
Steve H.
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Forums > Functional Verification > Assertion-Based Verification and Formal Analysis > forml verification on system level verification


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