hi there
I am looking for a 'proper' way to serially send data on a line (my application is ISO7816 but it could be any serial p[rotocol modeling)
Data are defined by

typedef enum byte {direct = 8'h3b, inverse = 8'h3f} t_InitChar;
typedef struct packed {
  bit td;
  bit tc;
  bit tb;
  bit ta;
  bit Α:0] nr_hist;
} t_FormatChar;

Which define the 7816 ATR patter

typedef struct packed {
  t_InitChar ts;
  t_FormatChar t0;
} t_atr;

I  can to send this patter by a s2p converter using the following

module p2s (in_array, out1, clk, reset, en);
parameter LE = 8;
   input clk, reset, en;
   input [LE-1:0] in_array;
   output      out1; 
   reg [LE:0]   par;
   reg         out1; 
   always @(posedge clk) begin
      if (reset)
          par <= 'b0;
      else if (en)
          par <= in_array;
      else
          {out1,par} <= {par,1'b0};
   end // always @ (posedge clk)
endmodule // p2s

and compose a pre-filled array by the structure members: still, I feel this is not the proper 'SystemVerolog'  way

Srry for this newbie question by a Verilog user which is moving into System verilog :-)

thanks