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Subject: Need help regarding interface usage in Systemverilog...
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prabhuk
Posts: 4
Online: User is Offline
9/20/2006 12:18 AM  
Hi All,

I'm having problem when i used the interface declaration in module. Pls see the error i got.
My UART DUT is a verilog module.

ncelab: *E,CUINMD (./sips_uart_bfm.sv,13|43): An interface connection must be connected to a Verilog parent (sips_uart_bfm).

module sips_uart_bfm(sips_uart_bfm_if  bfm_if, sips_uart_uart_if  uart_if, input reset,input clock);

This is an incompatible connection.  A Verilog interface must be connected
       to a port of a Verilog instance.  All other languages and connection
       types are disallowed.

Pls suggest me how to go about this.

Thanks & Regards,
Prabhu Kumar
tpylant
Posts: 87
Online: User is Offline
9/20/2006 9:30 AM  
I've seen this error when I tried to compile an intermediate file (i.e. not top level). I'm guessing you need to have a level above sips_uart_bfm that instantiates the sips_uart_bfm_if as well as sips_uart_bfm. Then you need to compile all three of those files (top, bfm, if) and that should resolve this problem.

Tim
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Forums > Functional Verification > SystemVerilog > Need help regarding interface usage in Systemverilog...


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