Hi,
I am sharing the little work i did on SystemVerilog. This can be the starting point for anyone new to the language. If you all can enhance this by adding your part, will really make an practical guide for the language.
// Program for Data-Types of SystemVerilog
// Author : Vivek Prasad
// Date : 15 Sep 2006
// Covers : shortint, int, real, time, reg, bit, logic, string, enum, struct
// class, functions, tasks.
module data_types;
//**************************Data-Types**************************************//
time dt_time = 1ms; // dt_time is defined as time variable.
shortint dt_decimal = 10; // 16-bit representation of decimal 10.
shortint dt_octal = 8'o17; // Octal "317" assigned to dt_octal.
bit Ε:0]dt_binary = 8'd42; // dt_binary will be "00101010".
logic Ε:0]dt_hex = 8'hAX; // 16-base-AB
byte dt_byte = "V"; // ASCII "V" character.
int dt_signed = -5; // 32-bit represen'n of -5 in one's compl.
real dt_real = 3.141; // Real number representation.
real dt_exp = 1.0e6; // Floating point representation.
reg Α:0]dt_reg = 4'b01XZ;// 4-value "reg" data-type.
// string dt_name = "{Vivek Prasad\n}"; // Not supported by ncsim5.6
// int dt_cast; // could not obtain the reult.
//************************Data-Types****************************************//
//****************************Enum********************************************//
typedef enum bit {NO,YES} boolean;
boolean dt_enum; // To use boolean as variable-type, use typedef.
assign dt_enum = YES;
//****************************Enum********************************************//
//****************************Struct******************************************//
typedef struct packed {
bit Ε:0] opcode;
bit ⎣:0]addr;
} IR; // To use IR as variable-type, use typedef.
IR dt_instr;
//****************************Struct******************************************//
//****************************Class*******************************************//
class adder;
int a;
int b;
int sum;
task add();
sum = a + b;
endtask
function void init();
a = 2;
b = 5;
$display("a=%d & b=%d",a,b);
endfunction
endclass
adder dt_add = new();
//****************************Class*******************************************//
//****************************Casting*****************************************//
// dt_cast = int'(3.141);
//****************************Casting*****************************************//
//****************************Initialization**********************************//
initial
begin
$display("Time Literal : %t\n",dt_time);
$display("Decimal Literal : %d\n",dt_decimal);
$display("Octal Literal : %o\n",dt_octal);
$display("Binary Literal : %b\n",dt_binary);
$display("Hex Literal : %h\n",dt_hex);
$display("Byte Literal : %h\n",dt_byte);
$display("Signed Literal : %d\n",dt_signed);
$display("Real Literal : %f\n",dt_real);
$display("Float Literal : %f\n",dt_exp);
$display("Reg Literal : %b\n",dt_reg);
// $display("String Literal : %s\n",dt_string);
$display("Enum Data-type : %b\n",dt_enum);
$display("Structure Example");
dt_instr.opcode = 8'h12;
dt_instr.addr = 24'habcdef;
$display("Struct Member1 : %h",dt_instr.opcode);
$display("Struct Member2 : %h\n",dt_instr.addr);
$display("Class Example");
dt_add.init();
dt_add.add();
$display("Sum = %d\n",dt_add.sum);
// $display("Casting = %d\n",dt_cast);
$finish;
end
//****************************Initialization**********************************//
endmodule
// Output, as on ncsim5.6
// Time Literal : 1000000
// Decimal Literal : 10
// Octal Literal : 000017
// Binary Literal : 00101010
// Hex Literal : ax
// Byte Literal : 56 // ASCII Value of "V"
// Signed Literal : -5
// Real Literal : 3.141000
// Float Literal : 1000000.000000
// Reg Literal : 01XZ
// Enum Data_type : 0
// Structure Example
// Struct Member1 : 12
// Struct Member2 : abcdef
// Class Example
// a = 2 & b = 5
// Sum = 7
Vivek Prasad |