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davyzhu
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1/15/2007 12:08 AM
Hi all, Is there any good methods to write SystemVerilog transaction sequence dependency constraint? For example, in below SV code, I want to always generate IDLE transaction after WRITE (i.e. WRITE after WRITE or READ after WRITE is illegal). //--- SV code start--- //define transactions typedef enum { WRITE=1,READ=2,IDLE=4} cmd_t; class Packet; ... rand cmd_t cmd; ... endclass Packet p; initial repert(20) begin p = new(); p.randomize(); end //--- SV code end--- Best regards, Davy

zeevk
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1/15/2007 1:26 AM
Posted By davyzhu on 1/15/2007 12:08 AM Hi all, Is there any good methods to write SystemVerilog transaction sequence dependency constraint? For example, in below SV code, I want to always generate IDLE transaction after WRITE (i.e. WRITE after WRITE or READ after WRITE is illegal). //--- SV code start--- //define transactions typedef enum { WRITE=1,READ=2,IDLE=4} cmd_t; class Packet; ... rand cmd_t cmd; ... endclass Packet p; initial repert(20) begin p = new(); p.randomize(); end //--- SV code end--- Best regards, Davy Hi Davy, Since you're looking just one step into the past, you could simply maintain a variable with the previous transaction type, use it in a constraint, and update its value after generating each new transaction. For example: cmd_t prev_cmd = WRITE; Packet p = new; initial repeat (20) begin // apply constraint assert( p.randomize() with {if (prev_cmd ==WRITE) cmd==IDLE } ) else $fatal; // do something with p here ... // update prev value for the next iteration prev_cmd = p.cmd; end Now, if you want to generate more interesting sequences of transactions with a certain structure to them, you should create a new class - a sequence, which generates a stream of transactions based on some "control knobs" you set in the class instance. You can then have multiple (inherited) subtypes of that sequence class, each generating a different kind of sequence, with different knobs. Regards, Zeev.

dbwalker0min
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1/15/2007 8:42 AM
Davy, In cases like this, I've been using the "pre_randomize" function as follows... //--- SV code start--- //define transactions typedef enum { WRITE=1,READ=2,IDLE=4} cmd_t; class Packet; ... rand cmd_t cmd; cmt_t last_cmd = IDLE; ... constraint c1 {last_cmd == WRITE -> cmd == IDLE;} function void pre_randomize(); last_cmd = cmd; endfunction endclass Packet p; initial repeat(20) begin p = new(); p.randomize(); end //--- SV code end If someone knows a better way to do this, I'd like to hear about it. David Walker

davyzhu
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1/16/2007 5:15 AM
Hi Zeev and David, Thanks a lot for the good ideas! I have tried David's program and all OK. And there is an small errata for above program. 1. Assume only one instance of the class at one time change "cmt_t last_cmd = IDLE;" to "static cmt_t last_cmd = IDLE;" 2. Change "function void pre_randomize(); " to "function void post_randomize(); " Best regards, Davy

nitin_sharma
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1/16/2007 5:38 AM
Hi Davy, One of the most powerful aspects of system verilog generation is the randsequence construct. It is a very powerful feature and is very useful in generation of sequences. It is also very scalable. I will post an example later today on how to use it. Nitin

zeevk
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1/16/2007 5:51 AM
Posted By davyzhu on 1/16/2007 5:15 AM Hi Zeev and David, Thanks a lot for the good ideas! I have tried David's program and all OK. And there is an small errata for above program. 1. Assume only one instance of the class at one time change "cmt_t last_cmd = IDLE;" to "static cmt_t last_cmd = IDLE;" 2. Change "function void pre_randomize(); " to "function void post_randomize(); " Best regards, Davy Hi Davy, Making the last_cmd field statis is dangerous - it will not work if you have several such generator threads running simultaneously, as all the packet class instances share the static last_cmd value. Thanks, Zeev.

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Forums > Functional Verification > SystemVerilog > SV transaction sequence dependency constraint?

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