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Subject: Verilog/SystemVerilog mixing ncsim Fatal error?
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davyzhu
Posts: 90
Online: User is Offline
2/08/2007 8:59 PM  

When I run Verilog/SystemVerilog mixing ncsim, there is Fatal Error.

//-----Linux-----

ncsim: *F,INTERR: INTERNAL ERROR

Observed simulation time : 0 FS + 0

-----------------------------------------------------------------

The tool has encountered an unexpected condition and must exit.

Contact Cadence Design Systems customer support about this

problem and provide enough information to help us reproduce it,

including the logfile that contains this error message.

  TOOL: ncsim   05.83-p002

  HOSTNAME: shpc035

  OPERATING SYSTEM: Linux 2.4.21-32.ELsmp #1 SMP Fri Apr 15 21:17:59 EDT 2005 i686

  MESSAGE: sv_seghandler - trapno -1

-----------------------------------------------------------------

***Current stack trace:

 -->[Don't Know      ] 0x83f5812        

 

//-----SunOS-----

ncsim: *F,INTERR: INTERNAL ERROR

Observed simulation time : 0 FS + 0

-----------------------------------------------------------------

The tool has encountered an unexpected condition and must exit.

Contact Cadence Design Systems customer support about this

problem and provide enough information to help us reproduce it,

including the logfile that contains this error message.

  TOOL: ncsim   05.83-p002

  HOSTNAME: sh11

  OPERATING SYSTEM: SunOS 5.8 Generic_117350-36 sun4u

  MESSAGE: sv_bushandler - SIGBUS fault address not odd (0x1a42)

-----------------------------------------------------------------

***Current stack trace:

 -->[Don't Know      ] 458578    sss_tag_dbstart      + 72e8   

 -->[Don't Know      ] 405b78    sss_tag_pvsstart     + 5d8    

 -->[Don't Know      ] 379f84    Strap_doAllEvents_   + 1c8c8  

 -->[Don't Know      ] 37abfc    Strap_doAllEvents_   + 1d540  

 -->[Don't Know      ] 15956d8          

 -->[Don't Know      ] 144e878          

 -->[Don't Know      ] 4099c4    sss_tag_misc1end     + 2394   

 -->[Don't Know      ] 40a74c    sss_tag_misc1end     + 311c   

 -->[CMD RUN/CMD Overhead] 38568     simcmd_run           + 73c    

 -->[CMD Overhead    ] 3a12c     simcmd_tag_runend    + 84     
dbwalker0min
Posts: 0
Online: User is Offline
2/09/2007 9:11 AM  
Davy,

I don't think it is a problem to mix Verilog and SystemVerilog --- I'm doing it now with similar problems. My problems have mostly been "internal errors" in the elaboration phase. I've often found that if I muck around with the code I can get it to elaborate.

I noticed you're running point release 2. Point release 3 is out and does appear to be better.

Good luck.

David Walker
ajeetha
Posts: 97
Online: User is Offline
2/09/2007 9:58 AM  
In most of such cases I would send the testcase to the vendor and seek assistance as I don't believe the "users" can resolve stack traces. If you get a clue of what might cause (by narrowing it down to say few combinations), then maybe we can help.

I would recommend you contact CDN support. Also try using latest patch/release - SV is new and hence the later the version you use, the better it is (in general)

HTH,  
Ajeetha, CVC
www.noveldv.com
davyzhu
Posts: 90
Online: User is Offline
3/19/2007 11:43 PM  
Hi,

I have tried the IUS-583-S003, the old problem pass. Thanks!

Best regards,
Davy
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Forums > Functional Verification > SystemVerilog > Verilog/SystemVerilog mixing ncsim Fatal error?


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