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indeb
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3/21/2007 1:32 AM
Hi All, I have a very basic qn - jus picking up system. verilog -> if the testbench is in system verilog and the top level is in vhdl - will both the modules be able to talk to each other? Many Thanks in advance, indeb

ajeetha
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3/21/2007 7:33 PM
Hi Indeb, Yes, this should work - though not defined by LRM per-se, many tools support this Mixed mode sim nicely. My experience with NC is few years old, even then it supported VHDL-Verilog cosim nicely. So at the worst case the following should work for you: SV_Testbench --> Verilog Top --> VHDL DUT Top Level in VHDL with say a SV Program instantiated also works in other simulators BTW. HTH Ajeetha, CVC www.noveldv.com

indeb
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3/21/2007 8:46 PM
Hi Ajeetha sorry jus a couple of qns -> what do you mean by LRM, NC, mixed mode sim - mixed mode simulator? co sim? I am using modelsim - for simulation - but not too sure about the model building - when I buid the model - what is actually executing the code - I am on vnc server - I use modelsim to trace the signals - debbugging - but not too sure on how the codes are being built into a model - any insight? Thanks a mil! indeb

ajeetha
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3/23/2007 9:31 AM
Posted By indeb on 3/21/2007 8:46 PM Hi Ajeetha sorry jus a couple of qns -> what do you mean by LRM, NC, mixed mode sim - mixed mode simulator? co sim? I am using modelsim - for simulation - but not too sure about the model building - when I buid the model - what is actually executing the code - I am on vnc server - I use modelsim to trace the signals - debbugging - but not too sure on how the codes are being built into a model - any insight? Thanks a mil! indeb LRM - Language Reference Manual NC - NCSIM (www.cadence.com) Do google search to learn more on these. Regards Ajeetha, CVC www.noveldv.com

indeb
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3/24/2007 6:06 AM
Hi Ajeetha - one more qn - is this declaration in sv correct? parameter Α:1] top_one3 = 3'b1; I need bits 1-3 to be high - Thanks in advance!

bryan
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indeb
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3/25/2007 3:27 AM
sorry I meant parameter Α:1] top_one3 =3'b1; is this okay? indeb

TAM
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3/25/2007 10:16 AM
Just to repeat what Bryan said... In SystemVerilog, if you don't specify enough bits in a constant, the leftmost bits will be set of zero. So 3'b1 will be the same as 3'b001. So you need to set all three bits high explicitly. 3'b111 or {3{1'b1}}. If you are just starting with the language, I'd strongly recommend that you get an introductory Verilog book. It'll pay off.

indeb
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3/25/2007 6:49 PM
hi all:) thanks - but my post seems to always mess up - what i meant was i need bits 1-3 to be high and bit 0 to be low - so i think parameter Α:1 ]top_one3 =3'b1 .........would mean bits 1-3 high and bit 0 low? if the numbers in the square brackets still appear as A and 1 - i meant, three : one thanks indeb

bryan
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3/26/2007 10:23 AM
Try 3:0 = 4'b1110 or 4'hE or 4'd14 Bottom line is this is basic Verilog. So getting a book a previously suggested would be a good idea. The qualifiers are working like you think. Please review the examples and you'll see important differences between what you keep typing and what other keep suggesting.

Regards, Bryan

indeb
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3/26/2007 11:15 PM
yes i agree - i deserve that - i was under really tight schdule and kinda forgot some things - and when i did come back and look at my posts - seems like ramblings n wish could remove them - but i dont seem to be able to edit/remove once i have posted)n before someone posts a reply)-> currently using HDL Programmin fundamentals VHDL & verilog by Nazeih M Botros thanks indeb

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