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Forums > Functional Verification > SystemVerilog

Subject: Replication Patterns
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dfechser
Posts: 11
Online: User is Offline
3/28/2007 3:59 PM  
Look what I got!

    preamble =   '{PREAMBLE_SIZE{40'hDDDDDDDDDD}};
                                |
ncvlog: *E,APTYPE (/lsi/ftc/yampa_design/users/dfechser/experimental/lib/lsi_uvc_lib/lsi_nrz/sv/lsi_nrz_package.sv,81|32): Assignment Pattern - replication patterns unsupported at this time (PREAMBLE_SIZE) [SystemVerilog].


...anyone know when ncverilog will support this (PREAMBLE_SIZE is a variable)?

Dave F.
dwalker@sirenza.com
Posts: 2
Online: User is Offline
3/28/2007 4:06 PM  
I'm assuming that PREAMBLE_SIZE is a parameter. In that case, you could try to add another set of brackets like


parameter PREAMBLE_SIZE=16;
...
preamble = '{{PREAMBLE_SIZE{40'hDDDDDDDDDD}};
....

David Walker
dfechser
Posts: 11
Online: User is Offline
3/29/2007 12:35 PM  
PREAMBLE_SIZE is an input to the "new" function and is used to set the size of the dynamic array.

When I added the extra brackets I get an error that says "Illegal operand for constant expression" which sounds closer than I was before. 

I need to figure out how to tell SV that the function input is a constant, I guess.
dfechser
Posts: 11
Online: User is Offline
3/29/2007 12:41 PM  
Hm, I tried "const ref" and "const ref int" and both give me the same error message:

"Illegal operand for constant expression"

Does anyone have any ideas?

What I have is a transaction with resizeable preamble, data, and flush fields so I want to set them in the new() function and use dynamic arrays to hold the parts.
Jim McGrath
Posts: 6
Online: User is Offline
3/29/2007 12:52 PM  
replication patterns are not currently supported, something like the following works in 5.8. not the most elegant, but the underlying implementation would need to do the same....

module temp;

parameter PREAMBLE_SIZE = 16;
bit preamble[]

initial
begin
preamble=new[PREAMBLE_SIZE]
for (int i=0; i preamble[i]=40'hDDDDDDDDDD;
end

endmodule
dwalker@sirenza.com
Posts: 2
Online: User is Offline
3/29/2007 1:14 PM  
If it's a parameter, why not do

------------------------------------
module temp;

parameter PREAMBLE_SIZE = 16;
bit [PREAMBLE_SIZE*40-1:0] preamble;

initial begin
preamble='{{PREAMBLE_SIZE{40'hDDDDDDDDDD}}};
end

endmodule
------------------------------------
It compiled for me in 5.83. I assume the OP wanted to pass it to a task as a parameter like

------------------------------------
module test;

// the dynamic array must be defined here because it is invalid in a task
bit preamble[]

task xxx(input int PREAMBLE_SIZE);


preamble = new[PREAMBLE_SIZE*40]

preamble = '{PREAMBLE_SIZE{40'hDDDDDDDDDD}};

endtask

initial begin
xxx(13);
xxx(10);
end

endmodule
------------------------------------

When I did this, I got the same error messages as the OP. I tried your for loop trick in the above and it worked OK.

David Walker
Jim McGrath
Posts: 6
Online: User is Offline
3/29/2007 1:25 PM  
yeah, my bad. The issue is with replication initialization which is not currently supported. ~jm
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Forums > Functional Verification > SystemVerilog > Replication Patterns


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