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Subject: generic task for hdl node force/release in system verilog
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unmesh
Posts: 1
Online: User is Offline
4/16/2007 8:12 AM  

i want to develop a generic task to force an hdl node inside the rtl.
the hdl path will be passed as a string to the task
eg: string s = "top.u_block1.u_block2.node_a";

this string will be passed as input to a task and the task should either force the value of the hdl path.
the hdl path should not be hardcoded. it should be only passed as a string. the string format can vary but it should only be a string.

is there any way to do this? i am using IUS583-s001. i don't see any example to do this in the documentation. also i am only using modules and not classes.

thanks and best regards

   Unmesh

Staff Engineer, Broadcom.
+91-9886404415
ajeetha
Posts: 97
Online: User is Offline
4/16/2007 10:41 AM  
Hi Unmesh,
      I believe you posted this in vguild as well: Here is a consolidated reply from my end:

 I believe this is doable with VPI - through vpi_handle_by_name and vpi_put in combination.

Are there good reasons to do this? ANy run time path generation sounds fancy, but can get you into trouble - imagine:

1. You run a sim till 100ms,
2. Do a fancy force like this and got a typo error
3. Bang! You hit an error and tool exits! Or sim fails!

It is better to let the path be statically checked at elaboration and let the sim run peacefully - Just MHO.
In any case I see 2 choices:

1. Use VPI as I suggested - IMHO, your best bet to be tool independent
2. Use TCL interface and get this done, fairly straight forward to do, though may not be as optimal as #1. This will be lot less work from your end:
  
HTH
Ajeetha, CVC
www.noveldv.com
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Forums > Functional Verification > SystemVerilog > generic task for hdl node force/release in system verilog


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