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Subject: SC and SV co-simulation in IUS?

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davyzhu
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4/19/2007 6:51 PM
Hi Cadence, Is there any SystemC and SystemVerilog in IUS co-simulation example available? BTW, will IPCM provide such a tutorial to show us how to do this work? Best regards, Davy

ajeetha
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4/21/2007 11:02 PM
While CDN shall answer that, what exactly are you looking to use it for? If it is "signal/pin" level interaction bet'n the 2 languages, it should work already as almost all tools support Verilog-SystemC co-simulation. Since SV is on top of Verilog, that basic level interface should work. If instead you are looking for a high level - transaction level interface bet'n them, I would imagine that to take a while. Mentor and Synopsys already support that sort of a thing from what I read. One idea will be to use DPI and use struct to pass the information across. It will be great to have class level interaction though LRM doesn't allow this today - unfortunate. Regards Ajeetha, CVC www.noveldv.com

davyzhu
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4/22/2007 11:39 PM
Hi Ajeetha, Thanks a lot for the information. I heard that IUS have SC/Verilog co-simulation environment, but I haven't used it before. Is it on pin layer or transaction layer? Any Cadence engineer can provide such information? Thanks! Best regards, Davy

jlrose
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4/23/2007 12:49 PM
Hi Davy, Yes, IUS does support SC/Verilog mixed language connection. Today, the connection is via signals (systemc signals connected to Verilog wires). The datatype mapping between systemc and verilog is fairly extensive; it is best to refer to the NCSC reference manual for detail. We do support passing packed structs across the language interface, so it is possible to send all of your data across the interface on a single wire. There are four different interfaces for connection between systemc and verilog: 1. module instantiation interface. This allows an sc module to be instantiated in verilog or vice versa. Mentor supports a similar interface as we have (we worked with Mentor early on to make sure that the interface was the same). 2. out-of-module reference interface. This interface allows a systemc signal to be bound to a verilog net/reg to put values, get values, or have sc processes sensitive to the verilog object. 3. out-of-module handle interface. This is a different interface from 2 in that there is no sc_signal involved. This interface allows you to read/write verilog objects. This is primarily used for backdoor access to verilog elements; for instances, verilog memories can be read/written from systemc using this interface. 4. direct task/function callling between systemc and verilog. This interface allows systemc processes to scedule verilog tasks (or call verilog functions) and vice versa. The NCSC reference manual provides a great deal of information on all of these interfaces. I hope this helps. Note that SystemVerilog adds a great deal of capability that NCSC needs to eventually work with: a number of new data types, variable ports, synchronization objects, dpi export tasks/functions, class objects, and more. Basic datatype support and dpi support will be the first special SystemVerilog things that NCSC works, but I would expect that eventually all of these things will work between languages in some form. john

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Forums > Functional Verification > SystemVerilog > SC and SV co-simulation in IUS?

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