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Subject: Reg : problem with reg declaration in IUS58
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mssajwan
Posts: 0
Online: User is Offline
4/22/2007 11:52 PM  
Hi all, I have declared a data member as reg. when i use it in an assign statement, I am supposed to get an error.Now 1. If i use the +sv switch i am not getting an error. 2. its showing an error if i do not use the +sv switch,which is as expected. I am using cadence IUS58, please clarify on this. thanks Manmohan
davyzhu
Posts: 90
Online: User is Offline
4/23/2007 12:24 AM  
Hi Manmohan,

If the data member is used on transaction layer, please declear it as bit (0/1) or logic (0/1/x/z).

Best regards,
Davy
mssajwan
Posts: 0
Online: User is Offline
4/23/2007 12:29 AM  
Hi Davy,

I have used the declaration inside a module

module test();
reg a,b;

assign a = b ? 1 : 0 ;

endmodule

in this code with +sv command line option its not giving me an error.
TAM
Posts: 56
Online: User is Offline
4/23/2007 6:45 AM  
In SystemVerilog, such code is now legal. Here's a snippet from the LRM:

SystemVerilog extends the functionality of variables by allowing them to be either written by procedural statements or
driven by a single continuous assignment, similar to a wire.

A wire can have multiple continuous assignments, like drivers on a bus. A reg can only have a single continuous assignment.
mssajwan
Posts: 0
Online: User is Offline
4/23/2007 7:07 AM  
Hi TAM,

thanks a lot for the reply. my doubt is now clear even though i have not checked the LRM but your comments
are sufficient.



thanks & regards
Manmohan Singh
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Forums > Functional Verification > SystemVerilog > Reg : problem with reg declaration in IUS58


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