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Many of you already received communications about the move of the Cadence user community into cadence.com. And many of you have already joined, with over 4000 registrations in the first two weeks.

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Michael A. Catrambone - Steering Committee Chairman
Distinguished Engineer
PCB/Mechanical
UTStarcom, Inc.

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Subject: SC-SV-Verilog interface
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dvp
Posts: 1
Online: User is Offline
4/23/2007 9:08 PM  
   How does the Cadence simulator NCSim handle the hierarchical interface between SystemC, SystemVerilog and Verilog2001. i.e. if the lower level modules are in different languages. e.g. worklib.entity:arch.

Regards,
-Deepak
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Forums > Functional Verification > SystemVerilog > SC-SV-Verilog interface


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