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Subject: Multiple interfaces with single driver in SV
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sam_kishore
Posts: 1
Online: User is Offline
6/01/2007 5:50 AM  
I have one interface with multiple clocking blocks which are actually different interfaces of the DUT.These interfaces differ their properties depending on the interface. for one interface the port is input for other same port is output. To solve this in SV, I can have an interface with different clocking block which defines the properties of different interface. Now the problem is I have a common driver which supports all these interfaces, so I should have a common interface instantiated inside the driver. Based on different modports,which is being passed through the construct of the driver, it should take the modport of that interface and work accordingly. Please let me know, how can I pass different modports of an interface through the construct to behave the mutiple instantiation of the driver accordingly? Sam
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Forums > Functional Verification > SystemVerilog > Multiple interfaces with single driver in SV


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