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Subject: "Automatic" keyword supported in NCverilog6.1?

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sundar_80
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7/07/2007 3:21 AM
Hello All, Do the system verilog keyword "automatic" is supported in ncverilog ver 6.1? I tried the following code program automatic test(FIFO_INF.TEST FIFO_INF_U1) // code endprogram The above gave me error, then i tried removing automatic, then the program worked fine. So want to know automatic" keyword is suported or not. Thanks & Regards, Quest Team

stephenh
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7/09/2007 2:18 AM
Hi Sundar. A "program" itself can't be "automatic", it just doesn't make sense since a program is like a special version of a module. Each program is instantiated in the simulation hierarchy, thus has its own scope and variable instances. Automatic is only referring to the program's tasks or functions, because these can be invoked in parallel (i.e. creating multiple threads). In this case automatic tells the simulator to keep separate copies of variables for each invocation of the task/function. It sounds like automatic program may not be supported, but you can achieve the exact same effect by declaring all the tasks/functions as automatic inside a normal program block. For example the following two forms should behave identically. This would also be clearer to anyone reading the code, since it's then obvious that each task/function has been declared automatic. program automatic p1; task t1; ... endtask endprogram program p2; task automatic p2; ... endtask endprogram Steve.

Steve H.

sundar_80
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7/24/2007 9:47 PM
Hello Steve, Thanks a lot for your reply and from your code i can understand clearly how we can achieve program automatic behavior. The basic reason for my query was in "SystemVerilog for Verification" by Chris Spear book, all the example program block contained "program automatic" when i tried to execute the same program in both cadence and modelsim the simulator gave error, so i was under the impression that modelsim and cadence doesn’t support automatic yet. But i have not tried the same example in VCS, anyways thanks a lot for your explanation. Sundar

ajeetha
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7/25/2007 9:07 AM
Hi Sundar, Automatic program is valid as per IEEE 1800 standard and I'm sure tools will support them in near future. I also recommend using automatic programs in my [b]SystemVerilog for Verification course [/b] that I deliver in Bangalore (See: www.noveldv.com). It makes life easier with several threads being spawned off with an advanced SV testbench. However as Steve said one can work it around as an interim solution. Here is LRM quote for your reference. [quote] program_nonansi_header ::= { attribute_instance } program [ lifetime ] program_identifier [ parameter_port_list ] list_of_ports ; [/quote] HTH Ajeetha, CVC www.noveldv.com

sundar_80
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7/27/2007 1:59 AM
Hello Ajeetha, Thanks a lot for your mail. Good to know about your recommendations which you are mentioning in the course, but can you able to run that program which uses the automatic program block? if so can you please let me know which tool you are using. Sundarraj

ajeetha
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7/27/2007 10:17 AM
Sundar, I didn't try your specific code, but we have used extensively automatic program construct during our VMM adoption book, see: www.systemverilog.us. I used VCS for the same. HTH Ajeetha, CVC www.noveldv.com

sundar_80
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7/29/2007 11:29 PM
Hello Ajeetha, THanks a lot i will soon try to get the VMM book from your website. Sundarraj

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Forums > Functional Verification > SystemVerilog > "Automatic" keyword supported in NCverilog6.1?