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Subject: Task implementation outside module or class?
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sundar_80
Posts: 20
Online: User is Offline
7/07/2007 3:31 AM  
Hello , Is it possible to decalre Tasks in a seperate file (without module or class) and use the task in a program or module. task.sv: File name ------------------ task test; $display ("In task"); endtask test.sv: Filename ------------------ program test(Interface) `include "task.v" initial test endprogram Inorder to accomodate above implementation what changes to be made in the code. Thanks in advance. Thanks & Regards, Quest Team
catchraghu
Posts: 0
Online: User is Offline
7/09/2007 3:46 AM  
i think u may have to import the module or package in which the program exists...
import::
this enables u to use all the module properties.... (data types ,functions, tasks.. etc)
dl_doulos
Posts: 9
Online: User is Offline
7/10/2007 6:11 AM  
Hi,

You can declare tasks (and functions) in a SystemVerilog package. The package contents can then be imported, one-by-one or with a wildcard, into any program or module. This is a cleaner solution than using Verilog `include. e.g.

//simple_package.sv
package simple_package;
   task test();
      $display("This is a test\n");
   endtask // test
endpackage // simple_package

//simple_program.sv
program simple();
   import simple_package::test;

   initial
     begin
        $display("Calling test..");
        test();
     end
endprogram // simple

The command "irun *.sv"  generates the following output:
Calling test..
This is a test

Regards,
Dave

  

David Long
Doulos
www.doulos.com
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Forums > Functional Verification > SystemVerilog > Task implementation outside module or class?


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