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Forums > Functional Verification > SystemVerilog

Subject: Declaring class outsside program block
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sundar_80
Posts: 20
Online: User is Offline
7/28/2007 3:10 AM  
Hello, Is it possible to declare class outside the program block like bellow? class gen; endclass program test; endprogram;
sundar_80
Posts: 20
Online: User is Offline
7/28/2007 3:14 AM  
Sorry for my earlier code for not following the rules, i have correct the format of the code now. 

 class gen; 
 endclass 
 program test; 
 endprogram;
Sundar
ajeetha
Posts: 97
Online: User is Offline
7/28/2007 4:40 AM  
Sundar,
 >> Is it possible to declare class outside the program block like bellow?

Yes, language allows it though I personally discourage it - atleast encapsulate them under packages. I know some debug tools today work best if classes are declared inside program.

HTH
Ajeetha, CVC
www.noveldv.com  
sundar_80
Posts: 20
Online: User is Offline
7/29/2007 11:28 PM  
Hello Ajeetha,
Thanks a lot for your mail, as you mentioned its always better to encapsulate it in package, i also feel that's the good practice.
But one query, if a class is encapsulated inside package is it possible to use the class itself, as far my knowledge about SV(i have very little knowledge) only task defined in the package can be used not the class is that correct?

Sundarraj
jagvinder
Posts: 8
Online: User is Offline
7/29/2007 11:34 PM  
Hi Sundar,
You can encapsulate the class inside a package and whenever you want to use this class, just "import" that package. You can import the package using following

import ::*;

then you can easily use the class and its all properties and methods which were declared in that package.


regards
Jagvin
jagvinder
Posts: 8
Online: User is Offline
7/29/2007 11:36 PM  
The command for importing the package is

import package_name::*;

sorry, i missed it in last mail.


regards
Jagvinder
sundar_80
Posts: 20
Online: User is Offline
7/29/2007 11:53 PM  
Hello Jagvinder,
Thanks a lot for your mail. I will try to use as you mentioned.

Sundarraj
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Forums > Functional Verification > SystemVerilog > Declaring class outsside program block


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