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sundar_80
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7/28/2007 3:16 AM
Hello, I have a query in what ways driver class to be implemented. I referred some example in the SystemVerilog book(I have not referred all examples only few), in all the example I referred the driver class is implemented in the program block, the major reason what iam thinking for the driver class to implement in the program block is, the driver need to drive value to the DUT, and the DUT interface block will be visible to the Driver class since the program Test block will have the interface/DUT signal as an input, so using a task in the driver class we can drive/monitor DUT pins. Driver class inside the program block ------------------------------------- program test(and_gate_if_u and_gate_if); class driver; task drive #10 and_gate_if_u.a <= 1’b0; #10 and_gate_if_u.b <= 1’b0; endtask endclass endprogram What I wanted I need to implement the Drive class outside the program block i.e in a separate file inorder to make the class generic so that in all the program TEST I will make use of Driver class; in that case I will be using tasks to drive DUT signals, in that case since iam implementing the drive class outside the class how I will have the access to the interface block or the signal blocks in DUT? To give a better idea of the above scenario I have given the code bellow, Driver class outside program block ----------------------------------- program test(and_gate_if_u and_gate_if); initial begin driver d1; d1 = new(); d1.drive end endprogram Driver Class ------------ class driver; task drive // Here I need to drive and_gate module signal ‘a’ and ‘b’ how to drive // Since this class is implemented in a different file the interface won’t // visible to this driver class endtask endclass Sundar

ajeetha
Posts: 97
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7/28/2007 4:55 AM
You can easily do this by passing a handle to virtual interface as argument to your driver constructor. Refer to any of VMM examples from our book (www.systemverilog.us), you will get the idea. class driver; virtual and_gate_if vif; function new(virtual and_gate_if vif); this.vuf = vif; endfunction : new <b> virtual </b> task drive; // Make this virtual for better reuse!! // Here I need to drive and_gate module signal ‘a’ and ‘b’ how to drive // Since this class is implemented in a different file the interface won’t // visible to this driver class vif.sig1 <= 1'b0; endtask endclass Looks like you will do lot better with a good methodology on top of SV. I would highly recommend you look at IPCM if you are using Cadence tools (looks like you are). Though I myself haven't seen it, I'm sure it addresses this stuff. FWIW - both AVM and VMM address this nicely. You may want to refer to them. Good Luck Ajeetha, CVC www.noveldv.com

sundar_80
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7/29/2007 11:23 PM
Hello Ajeetha, Thanks a lot for your mail. Currently iam using Cadence NCSIM 6.1 for my SV simulation, and noticed that some of the features is not been supported by the tool. Anways i will try to stick either to VMM or AVM. Sundarraj

sundar_80
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7/31/2007 12:49 AM
Hello Ajeetha, Thanks a lot for your reply, i have one more doubt can you please let me know why we are using virtual for and_gate_if? Sundarraj

ajeetha
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7/31/2007 6:44 AM
Since a class is dynamic object and interface being static, you need a "handle" to the interface, hence the virtual. May I recommend you attend a regular SystemVerilog class for better usage of the language - don't take me wrong, we are glad to assist over email on a forum like this, but for your productivity it is lot better to take up a class. We at CVC offer this in various forms - public, weekend, corporate etc. Drop me an email at cvc.training <> gmail.com if interested Cheers Ajeetha, CVC www.noveldv.com

tpylant
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8/03/2007 8:16 AM
The IPCM download (no charge product) contains an excellent user guide on putting together a reusable environment similar to VMM and AVM. However, it has a number of advantages such as multiple implementation styles (OO or non-OO), packaging for re-use from project to project, verificatioin component parameterization to allow re-use from block-chip-system, and a number of other features to ease the burden of the test writer. It directly addresses your question above and shows how to implement your sequence drivers so that data generation is separated from the actual driving of the DUT signals. Tim

tpylant
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8/03/2007 9:15 AM
Here is a website where you can find more information about IPCM: http://www.cadence.com/products/functional_ver/knowledge_system.aspx?DCMP=BAC-20070413p2cpreview

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Forums > Functional Verification > SystemVerilog > Driver class outside program block

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