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jaally
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8/22/2007 4:06 AM
Hello friends! I'm facing a problem while creating my Verification IP using SV language in URM environment. Right now, I'm just trying to up my master agent with these files: package.sv dut_interface.sv master_sequence_driver.sv master_interface.sv master_bfm.sv master_monitor.sv master_agent.sv dut_dummy.v dut_wrap.sv bus_interface.sv I got two errors"An interface connection must be connected to verilog parent" and "An interface port declaration must be connected"..... I couldn't able to go further....can anyone help me in this regards!? Thanks in advance! Regards, Jalli

stephenh
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8/22/2007 4:37 AM
Hi Jalli. You get these messages if you have not connected the SV interfaces correctly to your agent or DUT. If for example you DUT has a port declared as an interface, it must be connected to an interface of the same type. Without seeing your files it's hard to pinpoint the exact error, but I suggest you double check the connections from you top file going into the agent and DUT instances. You can send me the files if you don't manage to resolve it : stephenh cadence.com By the way, when you get an error message that you don't understand, try looking it up using the nchelp command. This usually gives some more details about the problem and how to solve it. For the two messages you described I pasted the nchelp commands and the output: [sve/main] $ <b>nchelp ncelab CUINMD</b><br> nchelp: 06.11-s003: (c) Copyright 1995-2007 Cadence Design Systems, Inc.<br> ncelab/CUINMD =<br> This is an incompatible connection. A Verilog interface must be connected<br> to a port of a Verilog instance. All other languages and connection<br> types are disallowed.<br><br> [sve/main] $ <b>nchelp ncelab CUIMBC</b><br> nchelp: 06.11-s003: (c) Copyright 1995-2007 Cadence Design Systems, Inc.<br> ncelab/CUIMBC = An interface port declaration may not be left unconnected.<br> [sve/main] $<br>

Steve H.

stephenh
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8/22/2007 4:45 AM
Sorry, the forum mashed my example. Here it is again: $ nchelp ncelab CUINMD nchelp: 06.11-s003: (c) Copyright 1995-2007 Cadence Design Systems, Inc. ncelab/CUINMD = This is an incompatible connection. A Verilog interface must be connected to a port of a Verilog instance. All other languages and connection types are disallowed. $ nchelp ncelab CUIMBC nchelp: 06.11-s003: (c) Copyright 1995-2007 Cadence Design Systems, Inc. ncelab/CUIMBC = An interface port declaration may not be left unconnected.

Steve H.

jaally
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8/22/2007 6:07 AM
Hi Steve!, Thanks a lot for your instant reply!!!!! I've seen your reply and I've sent the code to your mailID..i.e., "stephenh@cadence.com" I've corrected all the possiblities you've mentioned and also I use nchelp frequently for any error I get but for this problem I couldn't get the solution.....so plz help me in this regards. Please do letme know whether your mailID is proper or not as mentioned here. Thanks in advance, Regards, Jalli

tpylant
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8/22/2007 6:19 AM
The port connection to the UVC includes the dut_if. Therefore, make sure you have a top level that instantiates the dut_if and then connects it to the port of the UVC. Example: module top; ahb_interface dut_if (); // must instantiate interface ahb_uvc env (dut_if); // and connect it to module with interface port endmodule module ahb_uvc (interface dut_if); ... endmodule Tim

stephenh
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8/22/2007 6:48 AM
Hi Jally. I just replied to your mail with some more info. For the record, because you have only compiled the agent, and no env or testbench to instantiate the agent, the agent's interface is left unconnected, which is illegal in SystemVerilog. You should refer to the URM docs, and also the vr_xbus example that comes wit IPCM. You can find the vr_xbus example files under the IPCM installation, like this: IPCM/6.11/ipcm/urm_lib/sv_mb_ex_lib/vr_xbus Normally your testbench hierarchy would look something like this: sve (top module) \|- dut_if (instance of dut interface) \|- dut_wrapper (instance) \| \|- dut (the real dut) \|- sips_ahb_env (instance of the AHB env) \| \|- sips_ahb_master_agent \| \| \|- sips_ahb_master_monitor \| \| \|- sips_ahb_master_driver \| \| \|- sips_ahb_master_bfm \| \|- sips_ahb_slave_agent \| \| \|- (structure as per master agent) \|- any_other_interface_env \|- any_other_interface_master_agent \| \|- any_other_interface_master_monitor \| \|- ... \|- any_other_interface_slave_agent

Steve H.

jaally
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8/22/2007 9:40 PM
Hi Steve, Thanks once again!....I'll rectify my code and let you know very soon about it! Regards, Jalli

jaally
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8/23/2007 2:05 AM
Hi Steve, It worked out after I created any_other_env.sv and any_other_tb_top.sv......Error gone! Regards, Jalli

stephenh
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8/23/2007 4:37 AM
Hi Jalli. Glad to hear you fixed the problem :-) We always recommend that you build the whole URM structure (env, master and slave agents). If you do this, it has several advantages, including: 1) Consistent structure, so your code is more understandable. 2) You can develop the protocol without needing a real DUT (master agent talks to slave agent for verif env bring-up). 3) You can use the inactive part (e.g. slave agent) as a passive monitor of your DUT. This is most helpful when you have multiple slaves and you want coverage or checking on each slave DUT. There's loads more reasons, but those are a good start :)

Steve H.

jaally
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8/23/2007 11:46 PM
Hi Steve, Ok....I'll do accordingly....right now I'm concentrating on writing the code for slave agent! Thanks a lot for your suggestions and guidance!....I'll follow accordingly and will definetly seek your help if I get struck somewhere! Regards, Jalli

jaally
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8/28/2007 11:51 PM
Hello Steve, My environment is up but I've a warning based on system task which is shown as below: vb = $urm_get_message_verbosity(module_path); \| ncelab: W,MISSYST (./examples/urm_util_pkg.sv,263\|32): Unrecognized system task or function (did not match built-in or user-defined names) ΐ.7.4(IEEE Std 1364-2001)]. if ($urm_is_severity_defined()) \| ncelab: W,MISSYST (./examples/urm_util_pkg.sv,458\|30): Unrecognized system task or function (did not match built-in or user-defined names) ΐ.7.4(IEEE Std 1364-2001)]. sv = $urm_get_check_severity(module_path); \| ncelab: *W,MISSYST (./examples/urm_util_pkg.sv,464\|29): Unrecognized system task or function (did not match built-in or user-defined names) ΐ.7.4(IEEE Std 1364-2001)]. Can you please tell me in which system file these tasks are included so that I can remove these warnings by including those files!!? Thanks a lot in advance!, Jalli

zeevk
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8/28/2007 11:59 PM
Jalli, When using the SystemVerliog utilities in IPCM, the simplest way is to use the included *.args files. These will provide all the necessary command line options, including the VPI library you're missing. Use the apropriate file based on your compile flow: [The following is taken from the IPCM utiltilities guide - section 2.1.1] For irun: % irun -f $IPCM_HOME/util_lib/urm_util/sv/irun.args ... For ncvlog/ncelab/ncsim flow: % ncvlog -f $IPCM_HOME/util_lib/urm_util/sv/ncvlog.args ... % ncelab -f $IPCM_HOME/util_lib/urm_util/sv/ncelab.args ... % ncsim -f $IPCM_HOME/util_lib/urm_util/sv/ncsim.args ... For ncverilog: % ncverilog -f $IPCM_HOME/util_lib/urm_util/sv/ncverilog.args \ +tcl+"@source $IPCM_HOME/util_lib/urm_util/sv/urm_util.tcl ... Regards, Zeev.

jaally
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8/30/2007 11:10 PM
Hi Zeev, Thanks a lot for Ur info. but I wanna know one more thing! What shud i do if I'm not using IPCM methodology. I'm just using system verilog and I want to include vpi lib ? Regards, Jalli

stephenh
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8/31/2007 3:18 AM
Hi Jalli. You did originally say that you're using URM! URM is just a single component of IPCM, and I think Zeev meant to say URM, not IPCM in his reply. The libraries Zeev told you to use are specific to URM, so you're not pulling any extra bloat-ware ;-) In fact the URM module-based library is a very small amount of code, so it really doesn't hurt to compile it into your env. To answer your exact question, if you're only using pure SV language and not IPCM (URM?) then you won't need this VPI library because you aren't using the URM functions!

Steve H.

jaally
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8/31/2007 5:32 AM
Hi Zeev & Steve, Ok...I think I need to be clear of what exactly I'm looking for. I'm using URM methodology and creating specific components in SV language but i'm not using IPCM libraries or thier components. Also, since I'm using SV language and to support few already existing features I'm using two files i.e., "urm_defines.svh" and "urm_util_pkg.sv" files. So, when I include these files and compile using ncverilog in demo.sh I get these three warnings. I actually tried loading VPI library as Zeev suggested but failed in those attempts. And I couldn't find out where exactly I was wrong. So, please help me in this regards. Thanks in advance, Regards, Jalli

stephenh
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8/31/2007 6:06 AM
Hi Jalli. Is there any particular reason why you're not using the URM library functions? If you're worried about portability, note that the URM library is open source (i.e. you can see the code and compile it on other platforms). I assume that you just want access to the various constants and enum types that URM defines. In this case, I'd still suggest that you compile the whole URM library as Zeev showed you. This would help ensure that if you integrate a URM component from another team or vendor then it'll compile smoothly alongside your code. If you really cannot live with compiling all the URM files, and you are absolutely certain that you'll never ever need to integrate any other UVCs, then I suggest you look at the urm_util_pkg.sv and copy out the definitions that you require. Put them into a new file of your own, and just compile that. We really can't emphasise enough thought, that where customers do selectively apply bits of URM (and eRM before it), they tend to get into problems later on as their environments get bigger, or when they try to make legacy components fit with newer components later on... Always try to think about reuse and how your decisions may come back to haunt you later!

Steve H.

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Forums > Functional Verification > SystemVerilog > Help needed in creating URM using SV

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