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Subject: Differences b/w logic , reg & wire
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raghavendrap
Posts: 20
Online: User is Offline
8/24/2007 6:40 AM  
hi,

1.      i  know the differences between reg & wire...but i what to know the differences between logic , reg & wire clearly.

2.     When iam writing code in systemverilog using URM ..... i got a simple bug.. which iam pasting below & please let me know where to use reg , wire & logic in systemverilog coding.....


  
      
ncelab: *W,ENUMERR (./sv_module/sips_apb_env.sv,53|66): This
assignment is a violation of SystemVerilog strong typing rules for
enumeration datatypes.
            .PWRITE(dut_if.PWRITE),
                  |
ncelab: *E,ICDPAV (./sv_module/sips_apb_dut_wrap.sv,25|19): Illegal combination
of driver and procedural assignment to variable dut_if.PWRITE detected.
            .PADDR(dut_if.PADDR),
                 |
ncelab: *E,ICDPAV (./sv_module/sips_apb_dut_wrap.sv,26|18): Illegal combination
of driver and procedural assignment to variable dut_if.PADDR detected.
            .PWDATA(dut_if.PWDATA),      


... Raghavendra
TAM
Posts: 56
Online: User is Offline
8/24/2007 7:17 AM  
I think it would help the discussion if you would add the following info:
1. The declaration for dut_if.PWRITE
2. The port declaration for .PWRITE
ajeetha
Posts: 97
Online: User is Offline
8/24/2007 7:22 AM  
[quote]ncelab: *W,ENUMERR (./sv_module/sips_apb_env.sv,53|66): This
assignment is a violation of SystemVerilog strong typing rules for
enumeration datatypes.
.PWRITE(dut_if.PWRITE),[/quote]

You need to show us the declaration of:

PWRITE inside the DUT and
dut_if.PWRITE



[quote]ncelab: *E,ICDPAV (./sv_module/sips_apb_dut_wrap.sv,25|19): Illegal combination
of driver and procedural assignment to variable dut_if.PWRITE detected.

[/quote]

Again we need full declaration that shows:

1. Data type
2. Direction (I/O/IO)

to comment properly. From the clear error message it is clear that you have a "procedural assignment" - say inside task/function/initial PWRITE and perhaps a "net" connection from a block beneath.

Show us full code to help better. If it is too many lines, consider posting a tar ball or send via email ajeetha <> gmail.com

Interestingly I was doing some revamp of our (CVC, www.noveldv.com) SystemVerilog training material this week and found similar examples that we show during our classes.

Regards
Ajeetha, CVC
www.noveldv.com
raghavendrap
Posts: 20
Online: User is Offline
8/25/2007 12:03 AM  
thanks for your cooperation in helping me Tam..
           i have declared as
                    dut.v file....ouput reg PWRITE
               dut_interface.sv...logic PWRITE
                dut_wrap.sv--------- .PWRITE(dut_if.PWRITE)

                             dut_if is the dut interface name..........
TAM
Posts: 56
Online: User is Offline
8/27/2007 9:53 AM  
I've run a couple of tests using an interface, an always block and a submodule connection and I can't duplicate all of the behavior that you are seeing. :-(

One thing that has been explained to me that the SystemVerilog has two properties associated with a signal, its "type" and its "kind." The "kind" is the familiar Verilog "reg", "var" or "wire". The "type" is the data type, 4-state "logic", 2-state "bit", integer and real. You can leave out the "kind", as long as you have specified the "type". But if you do, then "reg" is assumed.

"logic PWRITE" is thus the same as "reg logic PWRITE".

In SystemVerilog, you are allowed one continuous assignment to a "reg", so you can connect that interface signal to a submodule's port. But if you also try to drive it using a behavioral assignment or connect it to a second port, you will get an error. So I can easily get the tool to complain about different combinations of drivers on a PWRITE signal that is implicitly declared as a "reg". But I can't quite get it to complain in the same way that you are seeing, so I can't really be sure what you might have done.

See what happens if you try declaring the signal as a wire.

wire logic PWRITE;

Or go thru your assignments and connections to that signal and make sure that they are all consistant with a "reg" kind of signal.
shalom
Posts: 13
Online: User is Offline
8/28/2007 12:10 AM  
This is not quite correct.

In SystemVerilog, logic and reg are both data types. In fact, they are the same data type.

So 'logic PWRITE' is like 'var logic PWRITE' and 'reg PWRITE' is like 'var reg PWRITE'.
raghavendrap
Posts: 20
Online: User is Offline
8/28/2007 4:53 AM  

i.e inorder to avoid the confusion of reg & wire....here in SV we are using "logic".
ajeetha
Posts: 97
Online: User is Offline
8/28/2007 12:11 PM  
Try making the PWRITE signal as "wire" instead of "logic" - "logic" doesn't allow multiple drivers while wire does. I just now fixed a similar problem in our inhouse code. I didn't do a thorough analysis so can't give you the exact rationale, maybe will do that tomorrow if I get time.

Cheers
Ajeetha, CVC
www.noveldv.com
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