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Forums > Functional Verification > SystemVerilog

Subject: Coverage of Enum Type Bins
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jagvinder
Posts: 8
Online: User is Offline
8/28/2007 11:33 PM  
Hi,
I have an issue while taking coverage of enum type bins.
I am using IUS 6.1. While compilation, warnings are coming for enum type bins.

Let me share the peice of code with you.
//TO SELECT FROM HALF DUPLEX OR FULL DUPLEX MODE OF TRANSMISSION
typedef enum {HALF, FULL } transmission_mode_t;
 
transmission_mode_t transmission_mode_cov;
 
covergroup packet_rxd @(packet_collected);
 
    HALF_DUPLEX_MODE_N: coverpoint transmission_mode_cov
    {
 bins HALF_DUPLEX_N = {HALF};
    }
 
    FULL_DUPLEX_MODE_N: coverpoint transmission_mode_cov
    {
        bins FULL_DUPLEX_N = {FULL};
    }
 
endgroup
 
packet_rxd_cg packet_rxd_instance = new(); 

The warning which is coming is

bins HALF_DUPLEX_N = {HALF};
                                 |
ncelab: *W,CUVBVE (/home/coverage.sv,146|26): Bin value type mismatch with coverpoint type.

        bins FULL_DUPLEX_N = {FULL};
                                 |
ncelab: *W,CUVBVE (/home/coverage.sv,151|33): Bin value type mismatch with coverpoint type.

This issue was not there with NCSIM 5.8.
Please help me to resolve this issue.

Regards
Jagvin
tpylant
Posts: 87
Online: User is Offline
8/29/2007 7:10 AM  
I ran your code in IUS5.83 and IUS6.11 which both worked. I don't have access to IUS6.1, so I can't verify your problem there, but since it works on IUS6.11, I'd advise to go ahead and download the latest version.

IUS0611USR4, Version: 06.11-s004 was just released this week, so it is a good time to download, especially if you are using the IUS low-power (CPF) capabilities.

Tim
jagvinder
Posts: 8
Online: User is Offline
8/29/2007 10:41 PM  
Thanks Tim,
but i am facing a serious issue while merging the functional coverage for my model.

Is it because of these warnings for enum type bins???? or somewhat else??????

While merging, it is giving some "checksum mismatch error". Although i am not changing my env at run-time, the error is coming.


Jagvin
tpylant
Posts: 87
Online: User is Offline
8/30/2007 8:25 PM  
I tried all possible combinations of mixing enums and randomization. The only way I could get the coverage loading to fail is if I modified the code. I was using IUS6.11-s002.

Tim
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Forums > Functional Verification > SystemVerilog > Coverage of Enum Type Bins


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