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Forums > Functional Verification > SystemVerilog

Subject: array initialization-1b (system-verilog)
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borgonov69
Posts: 0
Online: User is Offline
8/29/2007 9:14 AM  
Using the IUS 5.83 version, I'm trying to
compile these simple SV code lines:

parameter    ports_num                  = 4;      // ports number

integer px_num[ports_num-1:0]    // pixel num x port


initial
begin
  px_num[ports_num-1:0] = {default:4'h6};
end


and I got the following errors

file: /IPREUSE/DATABASE/INTERNAL/DIG/INPROGRESS/gborgo/simd_A0_a/config/../generic/rtl/svlog/shm.v
  px_num[ports_num-1:0] = {default:4'h6};
                                 |
ncvlog: *E,ILLPRI (/IPREUSE/DATABASE/INTERNAL/DIG/INPROGRESS/gborgo/simd_A0_a/config/../generic/rtl/svlog/shm.v,119|33): illegal expression primary Β.2(IEEE)].
        module simd.shm:v
                errors: 1, warnings: 0



Is it a problem of the IUS 5.83 version ?

Thanks
BR
Giampiero Borgonovo
tpylant
Posts: 87
Online: User is Offline
8/29/2007 10:53 AM  
The error is caused because you used specified a range on the assignment after already declaring the type. You have two choices for the fix. 

  integer px_num[ports_num-1:0] = '{default:4'h6};
or 

  integer px_num[ports_num-1:0]
  initial begin
    px_num = '{default:4'h6};
  end

For more examples, refer to IEEE1800, sec 8.13.

Tim
borgonov69
Posts: 0
Online: User is Offline
8/30/2007 1:42 AM  
This solution solves the syntax issue.

integer px_num[ports_num-1:0] = '{default:4'h6};


The issue is originated by the Esperan System verilog for designers manual (version 2.7) that I'm using
as reference.

Thanks.
BR
Giampiero
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Forums > Functional Verification > SystemVerilog > array initialization-1b (system-verilog)


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