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Forums > Functional Verification > SystemVerilog

Subject: input port (array type) issue
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borgonov69
Posts: 0
Online: User is Offline
9/04/2007 2:11 AM  
I have defined  in a module a input port of array type as following described:


module swfabr (

  .......
            input  logic                                                        req[ports_num-1:0],          
........

I got the compilation error:

ncvlog: *E,MEMDIO (/IPREUSE/DATABASE/INTERNAL/DIG/INPROGRESS/gborgo/simd_A0_a/config/../generic/rtl/svlog/swfabr.v,27|82): memory 'req' previously declared as input/output/inout.
        module simd.swfabr:v
                errors: 1, warnings: 0


but the req port is not previously decalared.


If I change the port direction from input to inout the error disappears.
Also if the port is declared as output there's no error.

Why ?

Thanks
BR
Giampiero
tpylant
Posts: 87
Online: User is Offline
9/04/2007 8:45 AM  
Your input declaration defines an unpacked array. This is not currently supported in IUS, so you have two choices to fix the problem.

1) Define as an unpacked array: input logic Ε:0] req

2) Use var keyword to define as variable instead of net: input var logic req Ε:0]

Tim
borgonov69
Posts: 0
Online: User is Offline
9/04/2007 9:15 AM  
1) I dont like to define a packed array for this type of signal (array of bus request).
2) Is it synthesizable in this case ? Which are the differences with a net keyword ?

Thanks
Giampiero
borgonov69
Posts: 0
Online: User is Offline
9/04/2007 9:19 AM  
When will the input unpacked array be supported by IUS ?
In case of parametric code, it seems useful.

Thanks
BR
Giampiero
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Forums > Functional Verification > SystemVerilog > input port (array type) issue


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