Friday, November 21, 2008     Register | Login | Search | Contact Us
     
   
     
     

Many of you already received communications about the move of the Cadence user community into cadence.com. And many of you have already joined, with over 4000 registrations in the first two weeks.

The new Cadence Community enhances the ability of Cadence users to connect and collaborate. In addition to moving the community into cadence.com -- enabling single sign-on for community, Sourcelink and Cadence events -- the new site is organized around nine technology segments, giving you easy access to product information, training, forums and blogs. Some of the new features include:
  • Ability to respond to posts via e-mail
  • Technology-specific blogs
  • Latest Web 2.0 social networking capabilities
  • Public profile options
  • Private messaging
  • Friends lists
Visit the new Cadence Community today at www.cadence.com/community and join the discussions!

Registration note: Due to the scope of the enhancements and the new SSO registration system, we were not able to migrate existing cdnusers.org member accounts. So new registrations are required, but this enables a broader set of functionality we think you'll enjoy.

Forum note: Under the guidance of forum moderators, we have taken the 20+ cdnusers.org forums and consolidated them into 11 forums on the new site. Posts have been brought over so you can leverage that posting history. CDNusers forums will be set to read only starting 7/30, and cdnusers.org will be redirected to the new community on 8/4.

Best regards,
Mike and Tom

Michael A. Catrambone - Steering Committee Chairman
Distinguished Engineer
PCB/Mechanical
UTStarcom, Inc.

Tom Diederich
Cadence Community Manager
Home
Forums
Forums > Functional Verification > SystemVerilog

Subject: array of parameters issue (IUS61)
Posting to forums is available to community members only.
Login or Register
Rate this topic:
   
Author Messages
borgonov69
Posts: 0
Online: User is Offline
9/07/2007 3:40 AM  
1) I found the following issue about the initialization of an array of parameters:


package simd_pack;

  parameter    ports_num                           = 4;       // ports number 
  parameter    [ports_num-1:0]px_num      = '{ports_num-1:8,default:4};    // pixel num x port

endpackage : simd_pack

when I print the values of the array I got:

INFO: px_num 0
INFO: px_num 0
INFO: px_num 0
INFO: px_num 0


Is it  an issue of the IUS 06.11-s004 version ?

2) If I use the following definition:

integer    px_num[ports_num-1:0]      = '{ports_num-1:8,default:4};    // pixel num x port

then  it works

INFO: px_num           4
INFO: px_num           4
INFO: px_num           4
INFO: px_num           8

but in this case I cannot pass the array element as parameter to a module, because I got the following
error:

    swf_bfm #(.port_id(i),.pxn(px_num[i]))  u_swf_bfm (
                                      |
ncelab: *E,NOTPAR (../tbench/tb_swf.v,157|38): Illegal operand for constant expression Β(IEEE)].

3) If I define the array as unpacked array, I got the known IUS limitation:

parameter    px_num [ports_num-1:0]     = '{ports_num-1:8,default:4};    // pixel num x port


parameter    px_num [ports_num-1:0]     = '{ports_num-1:8,default:4};    // pixel num x port
                    |
ncvlog: *E,SVARPA (/IPREUSE/DATABASE/INTERNAL/DIG/INPROGRESS/gborgo/simd_A0_a/generic/rtl/svlog/simd_pack.v,21|20): Unpacked array and string parameters are currently not supported.
parameter    px_num [ports_num-1:0]     = '{ports_num-1:8,default:4};    // pixel num x port

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

How can I solve the following issue ?
I'd need  to define an array of constants and to pass a single element of the array as parameter
of a module.


Thanks
BR
Giampiero
 
borgonov69
Posts: 0
Online: User is Offline
9/07/2007 5:06 AM  
1) parameter [ports_num-1:0]px_num = '{ports_num-1:8,default:4};
is a packed array, therefore the intialization above doesnt make sense.
borgonov69
Posts: 0
Online: User is Offline
9/07/2007 5:31 AM  
This is the solution:

parameter logic [ports_num-1:0]Ε:0]px_num = '{ports_num-1:0,default:4}; // pixel num x port

I have the headache to work with the packed array, when unpacked array (3) shall be the natural solution.

Giampiero
TAM
Posts: 56
Online: User is Offline
9/07/2007 11:14 AM  
Just as a follow-up.

The declaration "parameter [ports_num-1:0] px_num;" isn't either a packed or unpacked array of parameters. It is a single parameter "px_num" whose width in bits is being set to "ports_num". That is certainly how Verilog 2001 interprets it and I would expect that SystemVerilog remains backward compatible.

I don't know how the initializer "'{ports_num-1:8,default:4};" would be interpreted in that context. I imagine that it assigns each bit in the single parameter "px_num" to the given value. Since each initializer has its low order bit = 0, all "ports_num" bits of the single parameter were set to 1'b0.
Posting to forums is available to community members only.
Login or Register
Forums > Functional Verification > SystemVerilog > array of parameters issue (IUS61)


ActiveForums 3.6
     
Copyright 2006 Cadence Design Systems, Inc.