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Subject: About URM/UVC
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vlsi_dude
Posts: 55
Online: User is Offline
9/11/2007 7:31 AM  
Hello....... As per I know UVC has three layers: Layer 1: Contains BFM, Monitor Layer 2: Contains Sequence driver, Monitor Layer 3: Contains Multi-channel sequence, Scoreboard I had a verification environment written using eVC with eRM based, and I want to change the env. into system verilog env. with URM based. And I want to keep all eVC intact, so at which layer we have to change so that it become a system verilog env. with uRM based
nilaygoyal
Posts: 9
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9/11/2007 7:57 AM  
Hi dude,

You are correct on the layers. If you have a well defined eVC and you want to convert it into uRM based, you need to work with SystemVerilog at layer 3.

Basically, every eVC has all the three layers within itself. If you need to change the control of eVC from 'e' to SV you need to work at layer 3. You do not need to change anything, you need to add some logic at layer 3 to have the eVC controlled by SV.

There is a separate CAT for Incisive Plan to Closure. This question shall be included in that particular section as it is related to IPCM.

Regards,
Nilay Goyal
eInfochips Ltd.
eInfochips Ltd., India
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