Hi, all,
I am new to SystemVerilog, so I decided to start with simple things, like SVA, first.
However, there is still something I could not figure out.
I made an SVA checker, during compiling, I met this error message:
ncvlog: 05.83-s008: ........
ncvlog: *F, SVARRA:  SystemVerilog mode incompatible with array access option.
The code segment related to this problem I guess is:

module clk_div_checker(
   rst_n,
   ref_clk,
   div,
   input_clk,
   ...
);
parameter DIV_WIDTH = 6;
parameter DIV_MAX = DIV_WIDTH -1 ;
input rst_n;
input ref_clk;
inout [DIV_MAX:0] div;
input input_clk;
...
tri1 rst_n;
tri1[DIV_MAX:0] div;
...
integer ref_cnt;
integer check_idx;
reg   input_clk_latch;
...
always_ff @(negedge rst_n or posedge input_clk) begin
   if (!rst_n) check_idx <= 0;
   else ckeck_idx <= ckeck_idx + 1;
end
always_ff @(negedge rst_n or posedge ref_clk) begin
   if (!rst_n) input_clk_latch<= 0;
   else input_clk_latch <= input_clk;
end
...
clk_frequence: assert property (CLK_FREQUENCE) else
   $error("CLK_FREQUENCE: .....");
property CLK_FREQUENCE;
   @(posedge input_clk)
      disable iff (!rst_n)
         (ckeck_idx  >1) |-> ref_cnt == (div - 1);
endproperty
...

The ncvlog.args is:

-INCDIR $HOME_ENV/std_ovl
-INCDIR $HOME_ENV/verilog_dut/my_clk_checker
-INCDIR $HOME_ENV/verilog_dut
...
-DEFINE OVL_ASSERT_ON
-DEFINE OVL_COVER_ON
-DEFINE OVL_SVA
-DEFINE ASSERT_ON
...
-SV
...
// Source Files
$HOME_ENV/verilog_dut/dut.v
$HOME_ENV/verilog_dut/my_clk_checker/checker.v
...

I tried this with IUS 5.83 and IUS 6.11. Both of them give the same error message.
Have any idea what could be wrong? I really don't have any idea where to start checking.
Thanks.