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Subject: No run time error for out of boundry access to array
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avidan_e
Posts: 16
Online: User is Offline
12/27/2007 9:02 AM  
Hi, The following code: module x; bitΏ:0] y[] initial begin y = newΐ] yΎ] = 2; yΏ] = 3; for (int i=0; i<= y.size(); i++) $display(y[i]); end endmodule // x doesn't give a run time error when I'm accessing yΐ]. Instead it gives the following print out: 2 3 0 I believe this is a bug. best, Avidan
TAM
Posts: 56
Online: User is Offline
12/27/2007 10:45 AM  
In standard Verilog, out-of-bounds array access is permitted by the HDL language. The value returned is simply 'bx or the unknown value. This is the way that hardware would work, you can index with an invalid address and the hardware will return something, you just don't know what it will be.

Since you are using an array of 'bit', you won't see an unknown value returned since 'bit' is only 2-state. So instead you see 'b0 as the return value.

Here's what the SV LRM says in section 5.3.

If an index expression is out of the address bounds or if any bit in the address is X or Z, then the index shall
be invalid. The result of reading from an array with an invalid index shall return the default uninitialized
value for the array element type.
avidan_e
Posts: 16
Online: User is Offline
12/27/2007 1:42 PM  
Hmmm... Thanks, Avidan
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Forums > Functional Verification > SystemVerilog > No run time error for out of boundry access to array


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