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sebastian
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1/09/2008 5:35 AM
Hi guys, I have an question concerning modularization, but I have not found it in one of the following books: "Writing Testbenches using SystemVerilog" and "SystemVerilog for Verification". So, I hope you can help me. I have written much classes, which are all in ONE file so far, but this is not the target state I wish for this project. The problem is, that for example, one class instantiates another class and I don't know, how to separate the classes. Is a mechanism available, as C-Header-Files? I hope you can help me, because several smaller files are much better than one singe huge file. Thanks for your help! If the answer should be in one of the itemized books, please sorry, I haven't found it! Sebastian

dl_doulos
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1/09/2008 6:25 AM
Hi Sebastian, If you have a large number of classes to manage, I would suggest putting them in a SystemVerilog package (this works in a similar way to packages in VHDL). If you want to use a similar mechanism to C header files, you can always use the Verilog `include "filename" macro. e.g. in "pkg.sv" package pkg; `include "class1.sv" `include "class2.sv" ... endpackge To use package in module (usually in another file): module top; import pkg::*; //make all package items visible here ... endmodule ---------------------------- Hope that helps. Regards, Dave

David Long Doulos www.doulos.com

tpylant
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1/09/2008 7:07 AM
Dave answered the question about partitioning up the classes into smaller packages. That is definitely the way to go and then you can "import" the packages you need into the modules. Of course you will need to make sure that you pass the package files to the compiler before the modules that need to import them. I think you may have also asked about how to call a class that hasn't been defined in another class. The way to do that is to use typedef as in this example: typedef class future_c; class current_c; future_c f; ... endclass class future_c; ... endclass The class future_c can be in the same file as current_c or in another file as long as both classes are visible to the compiler during the same compilation run. Tim

sebastian
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1/09/2008 7:56 AM
Hi, thanks for the fast replies. I have tried so, but something seems to go wrong at compilation: the classes I exported to packages, are unknwon. The source code is: import pkg::* //make all package items visible here program testprogram; parameter MODE_FIX = 0; // and so on endprogram I try to compile with the following command: ncvlog -mess -status -sv testprogram.sv I have also tried the following: ncvlog -mess -status -sv testproam.sv pkg.sv I hope, the classes need not to be declared within the key word "program ..." Thanks for your help, alone I would be in a fix (is this correct English? :) ) Sebastian

tpylant
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1/09/2008 8:13 AM
You need to compile the pkg.sv file first, i.e. "ncvlog -mess -status -sv pkg.sv testproam.sv". Since you are importing "pkg::", I assume that the package name is "pkg", i.e. "package pkg; ... endpackage". The import statement does not have to be within the program block, however by putting it outside, all of the package declarations are visible to any modules/programs/etc. that follow the import statement. I personally do not recommend that because it follows poor coding guidelines and can cause unforseen problems. It is better to import the package into each module where you want to use it. However, if you want to ignore that advice for a legitimate reason, then you might as well put the import statemetn at the end of your package file, i.e. "package pkg; ... endpackage import pkg::;" Tim

sebastian
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1/10/2008 4:34 AM
Hi, the next problem has occured and I hope you will help me again. :) I have written a source code like this: program test(); // definition of class class_1 ........ // definition of class class_n class_1 one; class_n n; initial begin one = new; n = new; // do something endprogram : test It worked so far. To be able to put the classes into separate files, I have tried to put program test(); just before "class_1 one; Now, the compiler tells me: Unrecognized declaration 'class_1' etc. Chris Spear writes on his book:"SystemVerilog for verification" on page 69 (section 4.4): Zou can define a class in SystemVerilog in a program, module, package, or outside of any these. Classes can be used in programs and modules." So, what am I doing wrong??? I'm not able to find any error. Thanks for your patience! Sebastian

sebastian
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1/10/2008 4:40 AM
To make it worse, class_n instantiates an object of class_1. I hope, this will not be an additional problem! Sebastian

tpylant
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1/10/2008 7:12 AM
I think this is what you are looking for: package pkg; typedef class class_n; class class_1; class_n n; function new(); n = new(); endfunction endclass class class_n; endclass endpackage : pkg program test; import pkg::*; class_1 one; class_n n; initial begin one = new(); n = new(); end endprogram : test I also want to note that although the LRM states that you can put class definitions "outside of any of these", IUS only supports classes defined in program, module, or package. This should never be a problem since a package accomplishes the same thing but in a more reusable and structured format (see my previous post about using the import statement). Tim

sebastian
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1/11/2008 1:09 AM
Thanks! The forward declaration was the critical point, now it works! Sebastian

sebastian
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1/11/2008 3:33 AM
And yet another question, I'm sorry for this, but I'm unexperienced in Verilog, SystemVerilog AND verification in general, so this is very hard. I've read books about verification in general, without any specific language and books concerning only Verilog and SystemVerilog, but the questions are appearing during programming. So here's my question: I've separated the classes in single files and packed them together in one class (with help of the keywords typedef, `include and of course with the help of you all here. My next task is to connect to "top level classes" (as described in Spear: page 212 - 213 with interfaces, because at the moment, no DUV is available. Now, I'm very unsure and don't know how to realise this task. Shall I implement two program blocks inside a module which both gets the same interface? For example: module top; interface if_inst; program1 (interface if_inst.if_master); Environment env1; ...... endprogram program2 (interface if_inst.if_slave); Environment env2; endprogram endmodule Thanks for your great help, without this I wouldn't be able to get ahead. Have a nice weekend! Sebastian

tpylant
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1/11/2008 8:04 AM
The program blocks are instantiated but not defined within the top level module. I would recommend that each test be in its own file just like any other module. program test1(interface di);<br> ...<br> endprogram<br> <br> program test2(interface di)<br> ...<br> endprogram<br> <br> module top();<br> dut_interface di();<br> dut_mod dut();<br> test1 test(di);<br> endmodule<br> I would also recommend looking at the documentation and examples that are provided with the new OVM (Open Verification Methodology) release. The OVM library does a lot of the work of building the infrastructure for you and automates the building of the environment. The documentation will walk you through how to use it and the examples give you working code to start with. You can get the OVM download from http://www.ovmworld.org and also see more discussion at http://www.cdnusers.org/Forums/tabid/52/forumid/66/postid/5960/view/topic/Default.aspx. Tim

sebastian
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1/14/2008 5:11 AM
Thank you very much for your good advices, tpylant. Next question is, where to store the source file for the interfache. I've already found the error messages I get, here in the forum but they don't really help me. I will describe, the files I have so far: One package which contains all my classes. The classes are all stored in separate files and included in the package. The program containing my testbench, includes the package with the import command. So far, so good. I have then a topmodule, which contains the source of the interface and the toplevel module (as described by tpylant above). Furthermore I've written a simple testmodule which "simulates" the real device (actually only tests if interface is working). But I don't know how to compile these files and nobody around me can help. Because of this fact, I hope, you will help me. So far, my "makefile" looks like the following: #! /bin/csh -f ncvlog -mess -status -sv pkg.sv env_prog.sv ncelab -mess -status -snapshot TEST env_prog ncsim -mess -status TEST pkg.sv contains the include-commands of the different classes and env_prog contains the program (not the toplevel module). Again, thanks for your help! Sebastian

sebastian
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1/14/2008 6:50 AM
Ok. this problem is solved, I've got same other problems with simulation, but I think the infrastructur itself is ok. To avoid an infinite thread not related with the base topic any more, I will begin a new thread if I need help (and I think I will need help). Thanks again @dl_doulos and tpylant for your help! Sebastian

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