interface xram_if

  (output CLK, nRST);

timeunit 1ns;
timeprecision 1ps;

  logic Ε:0] AD;
  logic ALE;
  logic nWR;
  logic nRD;

  modport master (
    output nWR,
    output nRD,
    output ALE,
    inout AD,
    import write,
    import read
  );

  modport slave (
    input nWR,
    input nRD,

    input ALE,

  endtask // init

  task write (
    input t_xram_addr addr,
    input t_xram_data data
  );
  begin
   ....

  end

  endtask // write

  task read (
    input t_xram_addr addr,
    output t_xram_data data
  );
  begin
...

  end
 endtask

I want to instantiate it in a test bench, e.g.

  xram_if xramif (
    .CLK(MCLK),
    .nRST(nRST)
  );

and I need a master interface to drive my DUT (so there are modports
above)
My DUT does not support interfaces (it is Verilog 2001)
How do I specifiy
- which interface flavor (master or slave)
How doi I connect my interface to the DUT?

The following does not work ...

I think I am missing sopme big points here ...

  vdt_top i_vdt_top(
...
    .access_if_ale_i               (xramif.master.ALE),
    .access_if_nwr_i               (xramif.master.nWR),
    .access_if_nrd_i               (xramif.master.nRD),
...

    .access_if_ad_0                (xramif.master.ADΎ]),
    .access_if_ad_1                (xramif.master.ADΏ]),
    .access_if_ad_2                (xramif.master.ADΐ]),
    .access_if_ad_3                (xramif.master.ADΑ]),
    .access_if_ad_4                (xramif.master.ADΒ]),
    .access_if_ad_5                (xramif.master.ADΓ]),
    .access_if_ad_6                (xramif.master.ADΔ]),
    .access_if_ad_7                (xramif.master.ADΕ]),

...

);

module dut_wrapper(interface mif, sif);
  vdt_! top i_vdt_top( 
    ... 
    .access_if_ale_i (mif.ALE), 
    .access_if_nwr_i (mif.nWR), 
    .access_if_nrd_i (mif.nRD), 
    ...
  ); 
endmodule
module top;
  xram_if xramif_m (.CLK(MCLK), .nRST(nRST)); 
  xram_if xramif_s (.CLK(MCLK), .nRST(nRST)); 
  dut_wrapper dut (xramif_m.master, xramif_s.slave);
endmodule

module top;
  xram_if xramif (.CLK(MCLK), .nRST(nRST)); 
  dut_wrapper dut (xramif.master, xramif.slave);
endmodule

interface xram_if(...);
  ...
  wire  [`DATAW-1:0] AD
  logic [`DATAW-1:0] data_out;
  assign AD = !nWR ? data_out : 'z;
  ...
  task write(...);
    ...
    data_out = addr[`DATAW-1:0]
    ...
  endtask
  ...
endinterface