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ROOZ
Posts: 9
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6/02/2008 1:11 PM
Hi everyone, I have created a test bench which has some parameters and it instantiate a module which also has some parameters on its on. i pass the test bench's parameters to the parameters of the instance of the module and it works fine however when i try to override the test bench's parameter during the simulationg, it gives the following error: Error: (vsim-3852) Invalid override of parameter i do the following to simulate vsim -GWIDTH=16 -GADDR_BITSD=9 tb (WIDTH and ADDR_BITS are parameters of test bench which are passed to parameters of an instance of a module within the test case) this is how i defined my test bench parameter module tb #(parameter WIDTH=16,parameter ADDR_BITS=9); this is how i instantiated the module within the testbench generator#(WIDTH,ADDR_BITS) g1 (.*); could someone tell me what could i do during the simulation to override parameters of the test bench ?

tpylant
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6/02/2008 1:38 PM
I can't help you out much since vsim is the command for executing Mentor's simulator. However, with Cadence Incisive simulator it would be: % irun -defparam GWIDTH=16 -defparam GADDR_BITSD=9 tb Tim

ROOZ
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6/02/2008 2:32 PM
thanks alot for quick response to the thing is that i am sure that -G works fine with vsim because i tested it with another module but the actual mistrey to me is that when i try to override the top level file, it won't allow me to override the parameters. this is the actual error vsim 3852 vsim Message # 3852: # Once parameters for a module have been frozen, further redefinition # is not permitted. This error results from attempting to modify # parameters in an optimized design (compiled with -fast) by using # a separately compiled defparam or by specifying -G to vsim. i dont understand why i get this error for my test bench but not the module that instantiate within the test bench. what i mean is that the module instantiated within the test bench has its own parameters and outside the test bench i was able to test -G by overriding the parameters of that specific module. I have no clue why -G doesn't override in test bench too?

tpylant
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6/02/2008 3:21 PM
I think you did not understand my comment that this is a Cadence board and therefore you might not get much help in solving a problem for a non-Cadence product such as 'vsim'. Tim

ROOZ
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6/03/2008 10:02 AM
I understood what you said Tim, but i am limited to use Questa but as i mentioned before, vsim worked for me but in this special case is not working. i need a way to override the parameter during simulation using QuestaSim 6.3

ROOZ
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6/04/2008 11:12 AM
hey Tim, I finally got it to work, the only problem was the optimization which was occuring during the simulation the solution is -novopt. The -novopt switch instructs the compilation process to create the necessary information for simulations without optimization. this solved my problem. i hope it would help anybody else who is facing this problem.

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