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Subject: Implicit events in system verilog
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pandyk
Posts: 1
Online: User is Offline
7/03/2008 6:20 AM  
In specman, we can create events in both explicit and implicit way. Implicit creation event xyz is {@req;ΐ]@gnt}@clk_r; The same can be created explicitly by event xyz; tcm()@clk_r { while TRUE { @req; waitΐ] @gnt; emit xyz; }; } In system verilog, the events can be created explicitly. Is there a way I can create events implicitly in system verilog. Thanks
ajeetha
Posts: 97
Online: User is Offline
7/11/2008 8:09 AM  
Use SystemVerilog sequence for this - pseudo code:
<br>sequence xyz;<br>  @(posedge clk)  <span id="dnn_ctr467_NTForums_ntforums_post_lblReplyMessage" class="Normal">req; ##2;gnt;<br> endsequence : xyz<br>

Now "xyz" can be used an event in various contexts.

HTH
Ajeetha, CVC
www.noveldv.com
   
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Forums > Functional Verification > SystemVerilog > Implicit events in system verilog


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