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Forums > Functional Verification > SystemVerilog

Subject: Constraints, randomize bits in a vector
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ross.weber@unisys.com
Posts: 0
Online: User is Offline
1/26/2006 6:40 PM  
I want to randomly set a weighted random number of bits in a vector.

The code below randomizes the number of bits that are set based on the weights provided, but I haven't figured out how to insert the weighted random number of bits randomly in a vector.

I have some code commented out that was an idea I had, which may be wrong, but functions in constraints doesn't seem to be supported.

I'm using IUS5.6-s2. Thanks.

To run: ncverilog sv_test.v +sv

module sv_test();
class constraints;
bit ⎫:0] bit_vector;
rand bit ⎫:0] bit_vector_rand;
rand bit Γ:0] count;

constraint c0 {
count dist { Ώ:5]:/40,Δ:25]:/20,⎦:31]:/40 };
}

function int count_ones ( input bit Γ:0] w );
for( count_ones = 0; w != 0; w = w >> 1 )
count_ones += w & 1'b1;
endfunction

// constraint c1 {
// count==count_ones(bit_vector_rand);
// }

function void post_randomize();
bit_vector = {{32{1'b1}},{32{1'b0}}} >> (32-count);
$display("%d",count);
$display("x%h",bit_vector);
// $display("x%h",bit_vector_rand);
endfunction

endclass

constraints a = new;

integer num_iterations;

integer seed;
initial begin
num_iterations = 10;
if ($value$plusargs("SEED=%d",seed)) begin
$display("Using SEED=%d", seed);
end else begin
$display("Using default seed");
end
process::self.srandom(seed);
for (int i = 0; i < num_iterations; i++) begin
if ( a.randomize() == 0 ) begin
$display("%d error!",i);
end
end
end
endmodule
tpylant
Posts: 87
Online: User is Offline
1/27/2006 10:22 AM  
I used a randc to generate a non-repeatable number to use as the location to put the '1'.

module sv_test();

class constraints;
bit ⎫:0] bit_vector;
rand bit Γ:0] count;
randc bit Β:0] place;

constraint c0 {
count dist { Ώ:5]:/40,Δ:25]:/20,⎦:31]:/40 };
}

function void assign_bit ();
// $display("Assigning 1 to bit %d", place);
bit_vector[place] = 1;
endfunction

endclass

constraints a = new;

initial begin
integer num_iterations;
num_iterations = 10;

set_seed();

for (int i = 0; i < num_iterations; i++) begin
a.bit_vector = '0;
if ( a.randomize() == 0 ) begin
$display("%d error!",i);
end
place_randomize(a.count);
end

end

function void place_randomize(input bit Γ:0] bitcnt);
for (int i = 0; i < bitcnt; i++) begin
if (a.randomize(place)) begin
a.assign_bit();
end
end
$display("count = %d",bitcnt);
$display("vect = %b",a.bit_vector);
endfunction

function void set_seed ();
integer seed;
if ($value$plusargs("SEED=%d",seed)) begin
$display("Using SEED=%d", seed);
end else begin
$display("Using default seed");
end
process::self.srandom(seed);
endfunction

endmodule
ross.weber@unisys.com
Posts: 0
Online: User is Offline
1/27/2006 10:45 AM  
Great! Thanks!

Did you notice that the larger numbers didn't always set the right number of bits? Take a look below at the count of 31. It only set 27 bits. Bug?


ncsim> run
Using default seed
count = 26
vect = 01101111111111011101110111101111
count = 31
vect = 11111111111011100111111100111111
count = 2
vect = 00000000000000000000000011000000
count = 1
vect = 00000000000000010000000000000000
count = 29
vect = 11111111011111110111111111111110
count = 2
vect = 00000001000000000000000000000001
count = 27
vect = 11001010111111111111111111011111
count = 29
vect = 01111111111101101111111110011111
count = 2
vect = 00000000000010000000000000100000
count = 29
vect = 01111111111111110101111111110111
tpylant
Posts: 87
Online: User is Offline
1/27/2006 12:11 PM  
Good catch. The problem was caused because I never reset the place object, so it kept incrementing through the 32 choices. There might be a better way to reset a randc object, but I did it by deleting and recreating the class for each iteration. Here's the modification:

constraints a;

initial begin
integer num_iterations;
num_iterations = 10;

set_seed();

for (int i = 0; i < num_iterations; i++) begin
a = new;
a.bit_vector = '0;
if ( a.randomize() == 0 ) begin
$display("randomize a error!");
end
place_randomize(a.count);
a = null;
end

end
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Forums > Functional Verification > SystemVerilog > Constraints, randomize bits in a vector


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