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Subject: TB Simplification
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prasad_vc
Posts: 0
Online: User is Offline
8/20/2007 4:53 AM  
Hello All, In the process of verification, we develop many TestBenches those are useful for the module-level verification only. Once the module is verified, a new TB is developed for another module. Is there any alternative way to this approach, wherein we can reduce the time spent on the development of TB for each and every module? Is there any reusable approach for this? Any ideas or suggestions are welcome. -Vivek
stephenh
Posts: 77
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8/20/2007 7:16 AM  
Hi Vivek.

That's a very good question! Fortunately the URM (Universal Reuse Methodology) is designed specifically for this problem.
Whether you choose to code in e, SystemVerilog or SustemC, the methodology guides you through building a reusable testbench based on modular components. These guidelines have been developed through very close cooperation between Cadence and many customers over several years, so they really work.

The idea is to build everything in component form (e.g. bus interface components, sequence generators, protocol layering).
Each component is then used in a "testbench" that itself is designed to be plugged into a higher level testbench if needed.

You should take a look at http://myipcm.cadence.com/ for the online books that describe the methodology.
Also, get in touch with your local Cadence AE who can help you plan you verification.
Steve H.
ajeetha
Posts: 97
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8/20/2007 8:19 AM  
To add to what Steve just said, with recent OVM announcement, hopefully we will see more easily accessible guidelines soon. Having gone through VMM & AVM, I've been longing to learn eRM/URM, hopefully OVM will provide that opportunity.

Ajeetha, CVC
www.noveldv.com
stephenh
Posts: 77
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8/20/2007 8:43 AM  
I have not used AVM myself, but I believe it shares many principles with URM, so the merge of these two is a natural one.
I think perhaps that OVM will bring a lot of great automation to the very solid base laid down by the two methodology libraries.

Of course there is a lot more to good re-use than simply using a library such as URM, and the full Cadence Plan to Closure Methodology addresses the higher level concerns such as how to make integrate the different technologies (formal, coverage-driven, emulation etc), and how to use executable plans to automate so much of the day-to-day reporting and analysis that we (alas) have to do.
Steve H.
prasad_vc
Posts: 0
Online: User is Offline
8/20/2007 11:10 PM  
Thanks Steve, I'll go through the "myipcm" and also contact the cadence AE. -Vivek
stephenh
Posts: 77
Online: User is Offline
8/21/2007 3:13 AM  
Cool. You can of course ask questions here in the forum too, but I think if you're just starting down the road of re-use methodology, then a couple of hours spent with an experienced AE will give you the most value :-)
Good luck!
Steve H.
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