vlsi_dude
Posts: 55
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| 7/27/2007 11:29 PM |
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| hi dudes, can anybody help me.
my question is, while doing eVC with eRM methodology we r using sequences for stimulus generation and If we r not using eRM methodology then how can we generate stimulus? can anybody give me brief about it. |
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ajeetha
Posts: 97
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| 7/28/2007 8:41 AM |
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Sequence is a powerful means of achieving verification goal, but that's not the only way. Explain your scenario in English, someone will be able to help you code it in plain E. Understand that sequence is a construct internally built using plain E, so you can do the same thing with plain E - without sequences, though maybe hard. In general using a list and keep for each constraint you can achieve what you need.
Cheers
Ajeetha, CVC
www.noveldv.com |
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vlsi_dude
Posts: 55
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| 7/30/2007 3:31 AM |
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| Thanks a lot. One more thing, when i can use sequences and were not use in environment. You mention above that internally create e code. For that we need to import any file?. Lets i want to create environment for AHB eVC not with eRM compliant, can i write with sequences? if not why? if yes how? |
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stephenh
Posts: 77
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| 7/30/2007 5:42 AM |
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Whether or not you can use sequences in a non-eRM context *might* depend on just how different your environment is relative to eRM.
Can you explain why you are so keen to build a non-eRM compliant environment?
After all, eRM was developed from the best reuse practices of many customers. I can't think of any reason why you would need to avoid eRM.
If there's something you think can't be done in an eRM context, maybe the forum can help you see how it can be done?
Sequences use some e macros and base classes, so you would need to import the eRM package in order to use the sequence mechanisms, even if you're building a differently structured env.
Again, if you can give some more details on what you're actually trying to achieve, we can probably help... |
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Steve H. |
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vlsi_dude
Posts: 55
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| 8/03/2007 4:01 AM |
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Thanks a lot steve.
I am new to eVC.
Can u pls give me some brief information about how to create eRM complaint eVC's.
if u have any examples just provide me. |
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pjigar
Posts: 22
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| 8/03/2007 8:13 AM |
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Please read $SPECMAN_HOME/docs/pdf_docs/erm.pdf (eRM Developer Manual) for detailed instructions on how to create an eVC.
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Jigar Patel
Lead Consulting Engineer
Cadence Design Systems
jigar@cadence.com |
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stephenh
Posts: 77
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| 8/04/2007 11:31 PM |
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I can't give a short description that would do eRM justice! There are a number of things to consider with eRM, and a good place to start is to read the docs, as mentioned already by pjigar.
Cadence does have some template builder utilities that can produce a skeleton eVC tailored to your application (e.g. point-to-point bus, or multi-master/multi-slave bus). For these, I suggest you find your local Cadence AE and ask them to help you get started.
You will also find examples shipped with IPCM (the methodology kit from Cadence). These examples are complete eRM compliant eVCs that you can read about in the docs, and also run to see waveforms. If you don't already have it, IPCM is available off the Cadence website: http://downloads.cadence.com/.
Part of the eRM is the library of utilities like sequences, logging (message fn) and some base units for inheriting common functionality. Using these really helps your code to be efficient, and also makes it play nicely with any other eRM compliant eVC.
If you plan to reuse your eVC across different projects, then this becomes very important.
The other part of eRM is the architecture, the components you build (agent, monitor, sequence driver, bus functional model). eRM even gives recommendations about file naming and so on, to make it easy for people to support and maintain the code.
So as you see, there's a lot to explain about eRM! However, don't be afraid of it - the rules are all very simple, and logical.
With the help of your AE or the template builder, you'll be up and running in no time! :-)
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Steve H. |
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vlsi_dude
Posts: 55
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| 8/20/2007 6:16 AM |
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| Can any one help me on this. Any possible way to get throughput 100% for 2:1 bus arbiter. |
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Hilmar
Posts: 8
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| 8/21/2007 1:59 AM |
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Posted By vlsi_dude on 8/20/2007 6:16 AM
Can any one help me on this. Any possible way to get throughput 100% for 2:1 bus arbiter.
Hi Dude,
The documentation referenced by pjigar and Steve on eRM and sequences that are available in Specman and through sn_help.sh are quite elaborate on the subject. Assuming you've read that, what exactly is it you're having trouble with?
Regarding your 100% throughput, let's assume you've got a bus eVC in place with a BFM. Then you only need to setup a sequencing environment on top of that (the documentation is good on that) and then define the specific sequences you need, assuming you've got requirements on the stimuli for the arbiter.
Good luck,
Hilmar
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Hilmar v.d. K. |
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vlsi_dude
Posts: 55
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| 8/21/2007 4:06 AM |
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| Thanks a lot. In design point of view, any changes in arbiter, while doing verification can get 100% throughput. i have priority logic scheme algorithm. |
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Hilmar
Posts: 8
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| 8/21/2007 5:49 AM |
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| OK, let me rephrase my question: What exactly is it that you would like to have more information on? |
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Hilmar v.d. K. |
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vlsi_dude
Posts: 55
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| 8/21/2007 6:06 AM |
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| first i need to design 2 port arbiter with 100% throughput. i selected algorithm like round robin, priority logic. But all having plus r minus 50% throughput. so i think design fsm with no priority, we get 100% throughput. if you have any idea pls be share it. helpfull for me to design perfectly. |
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Hilmar
Posts: 8
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| 8/21/2007 6:16 AM |
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Ah, OK, I think there's a general sense of miscommunication going on here. Not a problem, but keep in mind that you're asking [i]design[/i] questions on a [i]verification[/i] forum.
You may benefit more from getting an experienced design consultant in your project to assist you, or search the web for RTL arbiter code examples.
Good luck!
Hilmar |
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Hilmar v.d. K. |
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vlsi_dude
Posts: 55
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| 8/21/2007 6:27 AM |
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| Thanks! c u later |
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vlsi_dude
Posts: 55
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| 8/29/2007 6:27 AM |
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hi guys,
anybody can help me on this issue. i trying to link specman with modlesim.
i'm trying this script.pl. specman invoking modelsim, but specman window is not enable fully.
And then from modelsim i can't give sn to control the specman because modelsim saying that invalid command.
system("specman -c \"load ~/env.e; save env.esv; write stubs -qvh");
system("vlib work");
system("vcom ./specman_qvh.vhd ~/name.vhd");
system("specview -p \" restore env.esv; test;\" vsim -keepstdout top_module");
so give me some comments to link specman with modelsim
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nls
Posts: 3
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| 8/29/2007 6:52 AM |
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Hi,
you're probably missing the pli routines.
try adding
-pli ${SPECMAN_HOME}/${BRUN_BUILD_OS}/libmti_sn_boot.so
to your specview call.
Nils |
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nls
Posts: 3
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| 8/29/2007 6:53 AM |
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| whoops, of course ${BRUN_BUILD_OS} must be ${SPECMAN_ARCH}, aka linux, solaris, etc... |
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pjigar
Posts: 22
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| 8/30/2007 8:00 AM |
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Do you have specman_reference instatiated in VHDL code e.g. in VHDL testbench?
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Jigar Patel
Lead Consulting Engineer
Cadence Design Systems
jigar@cadence.com |
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