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Subject: e-Support in Synopsys' VCS ?
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stelix
Moderator
Posts: 14
Online: User is Offline
11/08/2007 4:58 PM  
Truth, FUD or humor?

Rumor has it that Synopsys are working on supporting e in VCS! For those of you who haven't seen the thread on the Verification Guild, here is a link.

As an e user that can only be good news. Right? Or are we also going to see a VMM-for-e bomb, similar to the URM/VMM/AVM (and now OVM) SystemVerilog confusion? Will code be portable between simulators? How about eVCs?

Say the rumor is true, I'd be very interested to see what the e user base has to say.

Cheers,

-Stelix.

Stylianos Diamantidis
Verification Zone Moderator
CDNusers.org
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Forums > Functional Verification > e > e-Support in Synopsys' VCS ?


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