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SomeDude
Posts: 12
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1/30/2008 12:52 AM
Hi there, I'm having some sort of "constraint" problem, which some of you might have the answer to. The Scenario is the following, I use a virtual Sequence driver to drive frames onto a dynamic number of phy drivers. The goal is to be able to write a virtual sequence, which can be told on which phy it shall inject its sequences: extend virtual_seq_driver { !phy_driverΒ] : list of phy_driver_u; }; extend sve { virt_seq_driver : virtual_seq_driver is instance; connect_pointers() is also { for i from 0 to virtual_seq_driver.phy_driver.size() - 1 do { virt_seq_driver.phy_driver[i] = pointer_to_list_of_phy_drivers_somewhere[i].driver; }; }; }; sequence virt_seq using created_kind = virtual_sequence_t, created_driver : virtual_seq_driver; extend virt_seq { !phy_seq : some_phy_seq; keep phy_seq.driver = driver.phy_driver[phy_seq.seq_port_no - 1] -- ^^ This keep constraint results in a contradiction, because the seq_port_no is not properly constrained }; extend some_phy_seq { keep gen (seq_port_no) before (driver); seq_port_no : uint (bits:4); keep soft seq_port_no == 1; }; The code above does not really work, as seq_port_no is used with a somehow totally unconstraind value (actually PGen tries to use a range). If I comment the constraint on the driver and constrain seq_port_no while calling the sequence with extend MAIN virt_seq { do phy_seq keeping { .seq_port_no == 1; .driver == driver.phy_driver[.seq_port_no - 1] }; }; everything works peachy and I can constrain the sequence dynamically to any Phy Port I want to use. How can I constrain it properly, so I don't have to constrain the driver every time I driver the sequence? cheers for any solution

thinkverification
Posts: 28
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1/30/2008 11:20 PM
Hi there, Not sure if this is going to help, but about the "totally unconstrained" problem - try to check if the generated subtype has overridden the soft constraint on seq_port_no. Another option is to pre-generate the sequence (remove ! from !phy_seq : some_phy_seq;) so the sequence is pre-generated with the desired driver. To activate it use could start_sequence(). Again - not sure if this is going to really help :-) Yaron

Yaron Ilani VLSI Verification Specialist www.ThinkVerification.com

SomeDude
Posts: 12
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1/31/2008 12:19 AM
Hi there, thanks for your reply. As soon as I pregenerate the sequence, I cannot constrain it anymore in the body() section. The best solution for this whoel problem would be if it were possible to declare a list of seq !sequences[no_of_phys] : list of seq; and later simply do sequences[desired_port] keeping... However, as the do cannot handle this, and there's afaik no possiblilty like do append("sequence[",desired_port,"]") keeping it... I currently use the following: I declare only one sequence in the virtual sequence and constrain it to current_port_number, which is itself declared in the virtual sequence (not in the sequence itself, like I tried before): current_port_number : uint(bits:4); keep soft current_port_number == 1; !phy_sequence : phy_seq; keep phy_seq.driver == driver.phy_driver[current_port_number -1] That way I can simply set the current_port_number in the virtual sequence body() and it is automatically sent to the correct port. For now that's sufficient, but I'll still try to get the do macro to accept an indexed list_of_seq. greetings

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Forums > Functional Verification > e > dynamically assigning the drivers for a virtual seq

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