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Subject: Specman DUT error:
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balram.naik
Posts: 2
Online: User is Offline
2/22/2008 7:17 AM  
The protocol checkers suppose to work after transaction starts,
But getting fail even before transaction starts.

i.e.,It is checking before any actual transaction starts, with out any
events triggered that were supposed to trigger the protocol checks.

following error massage:

*** Dut error at time 60
Checked at line 81 in @X_xyz_protocol_checker
In X_xyz_monitor_u-@41 (unit: sys.xyz_evc.bus_monitor):

ERR_READ_XZ
Read went to X or Z during Address Phase

what could be the resone?.



Thanks in advance

Regads,
-Balram Naik
pjigar
Posts: 22
Online: User is Offline
2/22/2008 8:19 AM  
Can you post code snippet of the protocol checker? The error message is not helpful in seeing how the protocol check was activated and executed.
Jigar Patel
Lead Consulting Engineer
Cadence Design Systems
jigar@cadence.com
thinkverification
Posts: 28
Online: User is Offline
2/22/2008 4:05 PM  
I agree with pjigar, but if I had to take a guess I'd say you got unknown (X) or unconnected(Z) values in simulation or maybe the HDL ports are connected to wrong signals. Check the waveform.

Y.
Yaron Ilani
VLSI Verification Specialist
www.ThinkVerification.com
balram.naik
Posts: 2
Online: User is Offline
2/22/2008 11:10 PM  
Hi pjigar and Y,


Below, A small piece of protocol check code.

expect true((env.smp.sig_read.has_x() == FALSE) and
(env.smp.sig_read.has_z() == FALSE)) @normal_address_phase
else dut_error("ERR_READ_XZ\n",
"Read went to X or Z during Address Phase");

Here, normal_address_phase is a event, This event is emitted at the rising edge of clock at the start of each
Address Phase.

And HDL ports properly placed and in the wave forms, what i am getting are correct only.But in the specman console window getting error.

Here Protocol checks are starting at when simulation starts, but actually it is suppose to start with respect to event emit.

-M.B Naik
thinkverification
Posts: 28
Online: User is Offline
2/23/2008 1:52 AM  
Hmm.. Just to be 100% sure I would try to replace that piece of code with this:

on normal_address_phase {
message(NONE,"checking for X or Z values during address phase");
check that (env.smp.sig_read.has_z() == FALSE and env.smp.sig_read_has_x() = FALSE);
};

And see what happens...
1. Is the address phase event defined correctly?
2. If yes - maybe you're sampling the bus at transition point from X/Z to valid value


Hope this helps :-)


Yaron.
Yaron Ilani
VLSI Verification Specialist
www.ThinkVerification.com
pjigar
Posts: 22
Online: User is Offline
2/25/2008 6:47 AM  
I also think that event normal_address_phase is a suspect.
Jigar Patel
Lead Consulting Engineer
Cadence Design Systems
jigar@cadence.com
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Forums > Functional Verification > e > Specman DUT error:


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