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Subject: binding of simple inout ports to hdl wire (specman 6.2)
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arjuny
Posts: 7
Online: User is Offline
2/29/2008 2:16 AM  
Hi,
 
   I am trying to bind simple inout ports to hdl wires. Specman tool is giving the following error. (specman tool version 6.2)

           *** Error: Bound sets cannot have an external inout port with other
        external ports.
         sys.simple_evc.smp.sig_DBus: NCVLOG inout simple_port of uint (bits: 32)
                 Also externally connected to agent 'NCVLOG',
                 using hdl_path() 'DBus'

    The following is the sample code used for binding the simple port  

     sig_DBus : simple_port of uint(bits:32) is instance;
       keep soft sig_DBus.hdl_path() == "DBus";
       keep sig_DBus.declared_range() == "⎫:0]";
       keep sig_DBus.verilog_wire() == TRUE;
       keep bind(sig_DBus, external);

    What could be the reason for this error?  and how to get around from this problem?  

Thanks & Regards,
Arjun.


   


thinkverification
Posts: 28
Online: User is Offline
2/29/2008 1:45 PM  
Hi Arjun.
Is there another port in your system that has the same hdl_path?

Yaron
Yaron Ilani
VLSI Verification Specialist
www.ThinkVerification.com
arjuny
Posts: 7
Online: User is Offline
2/29/2008 10:05 PM  
Hi Yaron,

this is the only port that has this hdl path. Also it is the case for all the ports declared in the port map file. 

-Arjun
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Forums > Functional Verification > e > binding of simple inout ports to hdl wire (specman 6.2)


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